Digital frequency synthesizer with robust injection locked divider

Patent metadata

Field	Value
Publication number	US-10135452-B2
Application number	US-201715438438-A
Country	US
Kind code	B2
Filing date	Feb 21, 2017
Priority date	Feb 21, 2017
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

First claim

The invention claimed is:

1. A phased-locked loop (PLL) circuit comprising:
an injection locked digital digitally controlled oscillator (ILD) with an ILD control input element, an ILD injection input element and an ILD output element;
an adaptive control unit (ACU), wherein the ACU:
receives an error signal and a first modulation input signal, and
outputs an ILD control signal and a digitally controlled oscillator (DCO) control signal; and

a digital loop filter (DLF) wherein the DLF receives the error signal and outputs a filtered error signal to the ACU, wherein:
the ILD control input element receives the ILD control signal, wherein the ILD control word sets a natural oscillation frequency of the ILD, and
the ILD outputs a first output signal from the ILD output element, wherein the natural oscillation frequency sets a frequency of the first output signal, and the error signal comprises the first output signal.

2. The PLL circuit of claim 1 , further comprising a calibration mode, wherein the ACU determines the ILD control signal based on the filtered error signal, the error signal and the first modulation input signal.

3. The PLL circuit of claim 1 , further comprising a digitally controlled oscillator (DCO), wherein the ILD is configured to tune the natural oscillation frequency of the ILD to track a second output signal from the DCO.

4. The PLL circuit of claim 3 , wherein the ILD control signal and the DCO control signal comprise the first modulation input signal.

5. The PLL circuit of claim 3 , wherein:
the DCO includes a DCO input element and a DCO output element,
the DCO input element receives the DCO control signal,
the DCO outputs the second output signal at the DCO output element,
the DCO control signal received by the DCO input element sets a frequency of the second output signal,
the ILD injection input element receives the second output signal from the DCO output element, and
a phase of the first output signal from the ILD output element is synchronized to a phase of the second output signal from the DCO output element.

6. The PLL circuit of claim 5 , further comprising a time to digital converter (TDC), which includes a TDC output element, a first TDC input element and a second TDC input element, wherein:
the TDC outputs the error signal at the TDC output element,
the first TDC input element receives a reference frequency input signal, and
the second TDC input receives a loop feedback signal, wherein the loop feedback signal comprises the first output signal from the ILD output.

7. The PLL circuit of claim 6 , wherein a PLL output element is the DCO output element and the phase of the second output signal from the DCO output element is synchronized with a phase of the reference frequency input signal.

8. The PLL circuit of claim 3 , further comprising a multi-modulus divider (MMD), including an MMD control input element, an MMD injection input element, and an MMD output element and wherein:
the MMD control input element receives an MMD control signal comprising the sum of a second modulation input and a frequency control word (FCW),
the MMD injection input element receives the first output signal from the ILD output element, and
the MMD outputs a loop feedback signal, and wherein the MMD control signal sets the frequency of the loop feedback signal.

9. The PLL circuit of claim 7 , further comprising a delta-sigma (DS) unit, wherein the DS unit receives the sum of the second modulation input and the FCW and outputs the MMD control signal to the MMD control input element.

10. The PLL circuit of claim 8 , wherein the first modulation input is equal to an inverse polarity of the second modulation input.

Assignees

• Infineon Technologies Ag
• Milano Politecnico

Inventors

• Cherniak Dmytro
• Levantino Salvatore
• Tiebout Marc
• Nonis Roberto

Classifications

• H03B5/1212

  the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03B2201/0208

  the means being an element with a variable capacitance, e.g. capacitance diode · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title