Magnetoelectric memory cells with domain-wall-mediated switching
US-2018130511-A1 · May 10, 2018 · US
US11233192B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-11233192-B1 |
| Application number | US-202016988085-A |
| Country | US |
| Kind code | B1 |
| Filing date | Aug 7, 2020 |
| Priority date | Aug 7, 2020 |
| Publication date | Jan 25, 2022 |
| Grant date | Jan 25, 2022 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A hall bar device for a memory or logic application can include a gate electrode, a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer. For a memory application, the hall bar device can be written to by applying a pulse voltage across the gate electrode and one leg of the hall bar structure in the absence of an applied magnetic field; and can be read from by measuring a voltage across the one leg of the hall bar structure and its opposite leg.
Opening claim text (preview).
What is claimed is: 1. A hall bar device for memory and logic applications, comprising: a gate electrode; a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer, wherein a ferromagnetic state of the boron-doped chromia layer is controlled by a voltage applied across the gate electrode and one leg of the hall bar structure and is read out by a voltage across the one leg of the hall bar structure and its opposite leg while a read-out current is applied at one of the legs orthogonal to the one leg and its opposite leg to generate an in-plane current density. 2. The hall bar device of claim 1 , wherein: the hall bar structure comprises platinum. 3. The hall bar device of claim 1 , wherein: the gate electrode comprises Vanadium(III) oxide. 4. A memory device, comprising: an array of hall bar devices, each hall bar device comprising: a gate electrode; a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer, wherein a ferromagnetic state of the boron-doped chromia layer is controlled by a voltage applied across the gate electrode and one leg of the hall bar structure and is read out by a voltage across the one leg of the hall bar structure and its opposite leg while a read-out current is applied at one of the legs orthogonal to the one leg and its opposite leg to generate an in-plane current density. 5. The memory device of claim 4 , wherein: the hall bar structure of each hall bar device comprises platinum. 6. The memory device of claim 4 , wherein: the gate electrode of each hall bar device comprises Vanadium(III) oxide. 7. The memory device of claim 4 , further comprising at least one complementary metal oxide semiconductor (CMOS) device coupled to the array of hall bar devices. 8. A method of operating a hall bar device for a memory application, wherein the hall bar device comprises a gate electrode, a boron-doped chromia layer on the gate electrode; and a hall bar structure with four legs on the boron-doped chromia layer, the method comprising: writing to the hall bar device, the writing comprising applying a pulse voltage across the gate electrode and one leg of the hall bar structure in the absence of an applied magnetic field; and reading from the hall bar device, the reading comprising measuring a voltage across the one leg of the hall bar structure and its opposite leg. 9. The method of claim 8 , wherein the method is performed at a temperature of 300 K-400 K. 10. The method of claim 8 , wherein: the hall bar structure comprises platinum. 11. The method of claim 8 , wherein: the gate electrode comprises Vanadium(III) oxide.
Antiferromagnetic thin films, i.e. films exhibiting a Néel transition temperature (H01F10/3218 and H01F10/3268 take precedence) · CPC title
Materials of the active region · CPC title
using Hall-effect devices · CPC title
Antiferromagnetic materials, i.e. materials exhibiting a Néel transition temperature (H01F1/0036 takes precedence) · CPC title
details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.