Integrated circuits with embedded memory structures and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-11233191-B2
Application number	US-201816142432-A
Country	US
Kind code	B2
Filing date	Sep 26, 2018
Priority date	Sep 26, 2018
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming first and second conductive interconnects over a semiconductor substrate. The method includes depositing a conductive material over the first conductive interconnect. Also, the method includes forming a memory structure over the conductive material, wherein the memory structure has an uppermost surface distanced from the first conductive interconnect by a first height. Further, the method includes forming an interlayer dielectric over the memory structure and forming a conductive via coupled to the second conductive interconnect, wherein the conductive via has a second height over the second conductive interconnect less than the first height. The method also includes forming first and second contact plugs through the interlayer dielectric. The first contact plug contacts the memory structure and the second contact plug contacts the conductive via.

First claim

What is claimed is:

1. An integrated circuit with an embedded memory structure comprising:
a conductive interconnect disposed over a semiconductor substrate;
a conductive layer formed from cobalt material within an insulator layer and disposed on an upper surface of the conductive interconnect;
a memory stack disposed directly on an upper surface of the conductive layer and formed from cobalt material; and
a contact plug coupled to the memory stack, the contact plug having an upper surface substantially coplanar with an upper surface of the insulator layer and an adjacent contact plug within the insulator layer,
wherein the conductive interconnect includes a set of sidewalls that are substantially vertically aligned with sidewalls of each of the conductive layer, the memory stack, and the contact plug.

2. An integrated circuit with an embedded magnetic tunnel junction (MTJ) structure comprising:
a conductive interconnect disposed over a semiconductor substrate;
a bottom layer of highly conductive material within an insulator layer and disposed over the conductive interconnect;
a magnetic tunnel junction (MTJ) stack disposed over the bottom layer; and
a first contact plug contacting the MTJ stack, the first contact plug having an upper surface substantially coplanar with an upper surface of the insulator layer,
a second contact plug within the insulator layer having a lower surface substantially coplanar with a lower surface of the bottom layer of highly conductive material, and an upper surface substantially coplanar with the upper surface of the first contact plug and the upper surface of the insulator layer,
wherein the conductive interconnect includes a set of sidewalls that are substantially vertically aligned with sidewalls of each of the bottom layer of highly conductive material, the MTJ stack, and the contact plug.

3. The integrated circuit of claim 2 wherein the conductive interconnect and contact plug are formed from a same metal.

4. The integrated circuit of claim 2 wherein the highly conductive material is cobalt or a cobalt alloy.

5. The integrated circuit of claim 2 wherein the MTJ stack has sidewalls and further comprising a non-oxidizing liner on the sidewalls of the MTJ stack.

6. The integrated circuit of claim 2 wherein the conductive interconnect is a first conductive interconnect and the contact plug is a first contact plug, \ and wherein the integrated circuit further comprises:
a second conductive interconnect disposed over the semiconductor substrate;
the second contact plug coupled to the second conductive interconnect, wherein the highly conductive material is not located between the second conductive interconnect and the second contact plug.

7. The integrated circuit of claim 2 , wherein:
the MTJ stack has an uppermost surface at a first height over the semiconductor substrate;
the conductive interconnect is a first conductive interconnect and the contact plug is a first contact plug;
the integrated circuit further comprises:
a second conductive interconnect disposed over the semiconductor substrate;
a conductive via disposed over and coupled to an upper surface of the second conductive interconnect, the second contact plug being coupled to an upper surface of the conductive via; and
the conductive via extends away from the substrate and terminates at a second height over the substrate, wherein the second height is less than the first height.

8. An integrated circuit (IC) structure, comprising:
a conductive interconnect over a semiconductor substrate;
a cobalt-based conductive layer within an insulator layer, positioned on and contacting an upper surface of the conductive interconnect;
a memory stack positioned on and contacting an upper surface of the cobalt-based conductive layer; and
a contact plug coupled to the memory stack, the contact plug having an upper surface substantially coplanar with an upper surface of the insulator layer and an adjacent contact plug within the insulator layer,
wherein the conductive interconnect includes a set of sidewalls that are substantially vertically aligned with sidewalls of each of the cobalt-based conductive, the memory stack, and the contact plug.

9. The IC structure of claim 8 , wherein the conductive interconnect includes cobalt or a cobalt alloy.

10. The IC structure of claim 8 , wherein the memory stack comprises a magnetic tunnel junction (MTJ) stack.

11. The IC structure of claim 8 , wherein the memory stack has sidewalls and further comprising a non-oxidizing liner on the sidewalls of the memory stack.

12. The IC structure of claim 8 , wherein the conductive interconnect is a first conductive interconnect and the contact plug is a first contact plug, the adjacent contact plug is a second contact plug, and wherein the IC structure further comprises:
a second conductive interconnect disposed over the semiconductor substrate;
the second contact plug coupled to the second conductive interconnect, wherein the highly conductive material is not located between the second conductive interconnect and the second contact plug.

13. The IC structure of claim 8 , wherein the memory stack has an uppermost surface at a first height over the semiconductor substrate, the conductive interconnect is a first conductive interconnect and the contact plug is a first contact plug, the adjacent contact plug is a second contact plug, and wherein the IC structure further comprises:
a second conductive interconnect disposed over the semiconductor substrate;
a conductive via disposed over and coupled to an upper surface of the second conductive interconnect; and
the second contact plug coupled to an upper surface of the conductive via; and
the conductive via extends away from the substrate and terminates at a second height over the substrate, wherein the second height is less than the first height.

Assignees

• Globalfoundries Us Inc

Inventors

• Jacob Ajey P
• Ramanathan Eswar

Classifications

• H01L43/12

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H10N50/80 Primary

  Constructional details · CPC title

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title