Embedded memory in back-end-of-line low-k dielectric

Patent metadata

Field	Value
Publication number	US-10483121-B2
Application number	US-201815993608-A
Country	US
Kind code	B2
Filing date	May 31, 2018
Priority date	Feb 15, 2017
Publication date	Nov 19, 2019
Grant date	Nov 19, 2019

Abstract

A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.

First claim

The invention claimed is:

1. A device comprising:
a substrate comprising circuit components disposed on a substrate surface;
a plurality of interlevel dielectric (ILD) levels disposed on the substrate over the circuit components, wherein the plurality of interlevel dielectric (ILD) levels include a cell dielectric layer;
a storage unit of a memory cell between two adjacent ILD layers, wherein the storage unit is formed in the cell dielectric layer, the cell dielectric layer is disposed between the two adjacent ILD layers, the cell dielectric layer comprises a low-k dielectric material and is disposed over the storage unit; and
a polishing rate enhancer layer over the cell dielectric layer, the polishing rate enhancer layer comprising an oxide layer.

2. The device of claim 1 wherein the storage unit comprises a magnetic tunnel junction (MTJ) of a magnetoresistive random access memory (MRAM) cell.

3. The device of claim 1 wherein the low-k cell dielectric layer comprises SiCOH.

4. The device of claim 1 wherein the plurality of ILD levels comprises:
x ILD levels, wherein each ILD layer includes
a contact level V i−1 where I is the i th ILD level of the x ILD levels,
a metal level M i where I is the i th ILD level of the x ILD levels disposed over the contact level; and

wherein the two adjacent ILD levels between which the storage unit is disposed comprises
an upper metal level M j , which is a j th level of the x ILD levels, and
a lower metal level M j−1 .

5. The device of claim 4 comprises:
a cap layer disposed over the lower metal level M j−1 ;
a cell via dielectric layer disposed over the cap layer, wherein the cap layer and the cell via dielectric layer form a lower cell via layer; and
a lower storage unit contact plug disposed in the lower cell via layer.

6. The device of claim 5 wherein the cap layer comprises SiCNH.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Wang Lei
• Seet Chim Seng
• See Kai Hung Alex

Classifications

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10P95/062 Primary

  involving a dielectric removal step · CPC title

• H01L43/12

  Electricity · mapped topic

• H01L21/76819

  Electricity · mapped topic

• H01L21/31053 Primary

  Electricity · mapped topic