SiC epitaxial wafer, semiconductor device, and power converter

Patent metadata

Field	Value
Publication number	US-11233126-B2
Application number	US-201916718534-A
Country	US
Kind code	B2
Filing date	Dec 18, 2019
Priority date	Mar 1, 2019
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

A SiC epitaxial wafer includes a SiC substrate and a SiC epitaxial layer disposed on the SiC substrate. The SiC epitaxial layer includes a high carrier concentration layer and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carrier concentration layer. A difference in carrier concentration between the high carrier concentration layer and the low carrier concentration layers is 5×1014/cm3 or more and 2×1016/cm3 or less.

First claim

What is claimed is:

1. A SiC epitaxial wafer comprising: a SiC substrate; and
a SiC epitaxial layer disposed on the SiC substrate,
wherein the SiC epitaxial layer includes a high carrier concentration layer, and two low carrier concentration layers having lower carrier concentration than the high carrier concentration layer, and
being in contact with a top surface and a bottom surface of the high carrier concentration layer to sandwich the high carder concentration layer, and

a difference between carrier concentration of the low carrier concentration layers in regions of contact with the high carrier concentration layer and a maximum value of carrier concentration of the high carrier concentration layer is 5×10 14 /cm 3 or more and 2×10 16 /cm 3 or less;
wherein an occurrence of carrot defects in the SiC epitaxial layer is reduced by approximately 40% or more.

2. The SiC epitaxial wafer according to claim 1 , wherein
the high carrier concentration layer has constant carrier concentration along a thickness of the SiC epitaxial layer.

3. The SiC epitaxial wafer according to claim 1 , wherein
the high carrier concentration layer has, inside thereof, a maximum point at which the carrier concentration of the high carrier concentration layer has the maximum value, and
the carrier concentration of the high carrier concentration layer increases continuously from the top surface and the bottom surface to the maximum point along a thickness of the SiC epitaxial layer.

4. The SiC epitaxial wafer according to claim 1 , wherein
the high carrier concentration layer has a thickness of 0.1 μm or more and 0.5 μm or less.

5. The SiC epitaxial wafer according to claim 1 , wherein
the low carrier concentration layers have a carrier concentration of 1×10 14 /cm 3 or more and 1×10 16 /cm 3 or less.

6. A semiconductor device formed using the SiC epitaxial wafer according to claim 1 .

7. A power converter comprising:
a main conversion circuit including the semiconductor device according to claim 6 , and converting a power as input and outputting the converted power;
a drive circuit outputting, to the semiconductor device, a drive signal for driving the semiconductor device; and
a control circuit outputting, to the drive circuit, a control signal for controlling the drive circuit.

8. The SiC epitaxial wafer according to claim 1 , wherein
the low carrier concentration layers have a carrier concentration of 1×10 14 /cm 3 or more and less than 1×10 15 /cm 3 .

Assignees

• Mitsubishi Electric Corp

Inventors

• Sakai Masashi
• Mitani Yoichiro

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/36

  characterised by treatments done before the formation of the materials · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/3254

  Graded layers · CPC title