Electrochemical plating system and method of using

Patent metadata

Field	Value
Publication number	US-11230784-B2
Application number	US-201916677563-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Nov 30, 2018
Publication date	Jan 25, 2022
Grant date	Jan 25, 2022

Abstract

An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

First claim

The invention claimed is:

1. A method for performing an electrochemical plating (ECP) process, comprising:
contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited;
electroplating the metal on the surface of the substrate;
in situ monitoring an interface resistance between the electroplated metal and an electrolyte in the plating solution as the ECP process continues; and
adjusting a composition of the plating solution in response to the interface resistance being below a threshold resistance that is associated with a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate.

2. The method of claim 1 , wherein adjusting the composition of the plating solution comprises adjusting an amount of at least one organic additive in the plating solution.

3. The method of claim 1 , further comprising receiving a layout data of an integrated circuit to be manufactured on the substrate.

4. The method of claim 3 , further comprising calculating line-end densities of the plurality of conductive lines in a plurality of unit grid areas in the substrate based on the layout data.

5. The method of claim 4 , further comprising identifying the subset of conductive lines having the highest line-end density in a unit grid area of the plurality of unit grid areas.

6. The method of claim 5 , further comprising determining the threshold resistance based on empirical data.

7. A method of forming a semiconductor structure, comprising:
forming a plurality of contact openings in a dielectric layer over a substrate, the plurality of contact openings comprising a plurality of first contact openings in a first region of the substrate and a plurality of second contact openings in a second region of the substrate, the plurality of first contact openings having a highest line-end density in the plurality of contact openings;
forming a barrier layer along sidewalls and bottoms of the plurality of contact openings and over the dielectric layer;
forming a seed layer over the barrier layer; and
performing an electrochemical plating (ECP) process to fill the plurality of contact openings with a conductive layer, wherein performing the ECP process comprises:
in situ monitoring an interface resistance between an electroplated metal and an electrolyte in a plating solution as the ECP process continues; and
adjusting a composition of the plating solution in response to the interface resistance being below a threshold resistance that is associated with the highest line-end density.

8. The method of claim 7 , wherein forming the plurality of contact openings in the dielectric layer comprises etching the dielectric layer using an anisotropic etch.

9. The method of claim 7 , further comprising removing portions of the conductive layer, the seed layer and the barrier layer from a top surface of the dielectric layer.

10. The method of claim 7 , wherein performing the ECP process further comprises applying a bias between the substrate and an anode positioned in the plating solution.

11. The method of claim 7 , wherein performing the ECP process further comprises comparing the interface resistance with the threshold resistance.

12. The method of claim 1 , further comprising determining the threshold resistance using a layout data of an integrated circuit.

13. The method of claim 12 , wherein determining the threshold resistance comprises:
extracting a subset of the layout data corresponding to a plurality of conductive lines for a metallization layer from the layout data of the integrated circuit;
dividing the substrate into a plurality of unit grid areas;
calculating a line-end density of the plurality of conductive lines for each unit grid area of the plurality of unit grid areas;
identifying a subset of conductive lines in a unit grid area of the plurality of unit grid areas having the highest line-end density; and
determining the threshold resistance below which voids are formed in the conductive lines having the highest line-end density.

14. The method of claim 1 , wherein adjusting the composition of the plating solution comprises increasing an amount of at least one organic additive in the plating solution.

15. A method of forming a semiconductor structure, comprising:
depositing a dielectric layer on a substrate;
etching the dielectric layer to form a plurality of contact openings having different line-end densities in the dielectric layer, a plurality of first contact openings in the plurality of contact openings having the highest line-end density;
forming a seed layer along surfaces of the plurality of contact openings;
contacting the seed layer with a plating solution comprising a salt of a metal, an organic additive and an electrolyte;
depositing the metal onto the seed layer by electroplating;
in situ measuring an interface resistance between the electroplated metal and the electrolyte as the metal being deposited; and
increasing a concentration of the organic additive in response to the interface resistance being below a threshold resistance below which voids are formed in the plurality of first contact openings, wherein the threshold resistance is determined using a layout data of an integrated circuit.

16. The method of claim 15 , wherein the organic additive comprises a suppressor, an accelerator, a leveler, or combinations thereof.

17. The method of claim 15 , wherein determining the threshold resistance comprises:
extracting a subset of the layout data corresponding to a plurality of conductive lines for a metallization layer from the layout data of the integrated circuit;
dividing the substrate into a plurality of unit grid areas;
calculating a line-end density of the plurality of conductive lines for each unit grid area of the plurality of unit grid areas;
identifying a subset of conductive lines in a unit grid area of the plurality of unit grid areas having the highest line-end density, wherein the subset of conductive lines correspond to the first contact openings; and
determining the threshold resistance based on empirical data.

18. The method of claim 15 , further comprising comparing the in situ measured interface resistance with the threshold resistance prior to increasing the concentration of the organic additive.

19. The method of claim 15 , wherein the interface resistance is monitored using a sensor.

20. The method of claim 19 , wherein the sensor is an ohmmeter or an impedance meter.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Nian Jun-Nan
• Jangjian Shiu-Ko
• Wang Ting-Chun
• Lee Ing-Ju

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/043

  for electroplating · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10P14/47 Primary

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• C25D17/00

  Constructional parts, or assemblies thereof, of cells for electrolytic coating · CPC title