Semiconductor device with a trench electrode provided inside a trench formed on an upper surface of the semiconductor substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11227916-B2
Application number	US-201815934896-A
Country	US
Kind code	B2
Filing date	Mar 23, 2018
Priority date	Jun 9, 2017
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

According to an embodiment, a semiconductor device 1 includes a semiconductor substrate 50 including an upper surface, a trench electrode 22 provided inside a trench 20 formed on the upper surface, and a trench insulating film 21 provided between the trench electrode 22 and the semiconductor substrate 50. The semiconductor substrate 50 includes a first semiconductor layer of a first conductivity type, a lower end of the trench electrode 22 reaching the first semiconductor layer, a deep layer 19 of a second conductivity type partially provided on the first semiconductor layer in contact with the trench insulating film 21, a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer 19 in contact with the trench insulating film 21, and a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer 19.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate comprising an upper surface;
a trench electrode provided inside a trench formed on the upper surface; and
a trench insulating film provided between the trench electrode and the semiconductor substrate, wherein
the semiconductor substrate comprises:
a first semiconductor layer of a first conductivity type, a lower end of the trench electrode reaching the first semiconductor layer;
a deep layer of a second conductivity type provided on a portion of the first semiconductor layer, and in contact with the trench insulating film;
a second semiconductor layer of the second conductivity type provided on the first semiconductor layer and on the deep layer, and in contact with the trench insulating film; and
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer above the deep layer,

wherein
the trench electrode extends along a first direction in a plane parallel to the upper surface of the semiconductor substrate,
a plurality of deep layers, a plurality of second semiconductor layers, and a plurality of third semiconductor layers are provided, the deep layers being spaced apart from each other along the first direction, the second semiconductor layers being spaced apart from each other along the first direction, and the third semiconductor layers being spaced apart from each other along the first direction,
the semiconductor device further comprises:
an interlayer insulating layer provided on the semiconductor substrate; and
a wiring layer provided on the interlayer insulating layer,

the wiring layer is connected to the second semiconductor layers via a plurality of contacts provided inside a plurality of though grooves penetrating the interlayer insulating layer above the second semiconductor layers, and
a position of a lower end of a contact and a position of an opening of the trench are substantially equal in a direction orthogonal to the upper surface of the semiconductor substrate.

2. The semiconductor device according to claim 1 , wherein
a length of the third semiconductor layer in the first direction is less than a length of the deep layer in the first direction.

3. The semiconductor device according to claim 2 , wherein
the plurality of deep layers are provided on the first semiconductor layer; and
the plurality of third semiconductor layers are provided on the second semiconductor layer, the third semiconductor layers being provided above corresponding deep layers along the first direction, and
in the first direction, there are no third semiconductor layers provided above the first semiconductor layer between adjacent deep layers.

4. The semiconductor device according to claim 1 , wherein
a length of the third semiconductor layer in the first direction is substantially equal to a length of the deep layer in the first direction.

5. The semiconductor device according to claim 1 , wherein an impurity concentration of the deep layer is higher than an impurity concentration of the second semiconductor layer.

6. The semiconductor device according to claim 1 , wherein the third semiconductor layer overlaps only a portion of the deep layer.

7. The semiconductor layer according to claim 1 , wherein the deep layer and the third semiconductor layer overlap only a portion of the first semiconductor layer.

8. The semiconductor device according to claim 1 , wherein
a plurality of trench electrodes are provided,
a portion between adjacent trench electrodes comprises the first semiconductor layer, the deep layer, the second semiconductor layer, and the third semiconductor layer, and
a floating layer of the second conductivity type is provided on a portion other than the portion between adjacent trench electrodes.

9. The semiconductor device according to claim 1 , wherein
a plurality of trench electrodes are provided,
the plurality of trench electrodes includes a first and a second trench electrode,
the first semiconductor layer, the deep layer, the second semiconductor layer, and the third semiconductor layer are in contact with the trench insulating film provided around the first trench electrode, and
the semiconductor device further comprises a floating layer of the second conductivity type provided around the second trench electrode in contact with the trench insulating film.

10. The semiconductor device according to claim 1 ,
wherein
the wiring layer is connected to the second semiconductor layer via a contact provided inside a contact groove formed in the second semiconductor layer.

11. The semiconductor device according to claim 1 , wherein
a length of the deep layer in the first direction is substantially equal to a length of the second semiconductor layer in the first direction.

12. The semiconductor device according to claim 1 , wherein a portion of the first semiconductor layer is not overlapped with the deep layer, the second semiconductor layer, and the third semiconductor layer.

13. The semiconductor device according to claim 1 , wherein
the plurality of deep layers are provided on the first semiconductor layer,
the plurality of second semiconductor layers are provided on the first semiconductor layer and the plurality of deep layers,
the plurality of third semiconductor layers are provided on the plurality of second semiconductor layers and the plurality of deep layers, and
in the first direction, no second semiconductor layer and no third semiconductor layer is provided above the first semiconductor layer between adjacent deep layers.

Assignees

• Renesas Electronics Corp

Inventors

• Kanda Ryo

Classifications

• H10D62/393 Primary

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D12/461

  having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title