Width adjustment of stacked nanowires

Patent metadata

Field	Value
Publication number	US-10069015-B2
Application number	US-201615276372-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Sep 26, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

First claim

What is claimed is:

1. A method of forming a semiconductor device, comprising the steps of:
forming an alternating series of sacrificial and active layers on a wafer;
patterning the alternating series of sacrificial and active layers into at least one nano device stack;
forming a dummy gate on the at least one nano device stack;
patterning at least one upper active layer in the at least one nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate;
forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned;
forming source and drain regions on opposite sides of the at least one nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers whereby the spacers electrically insulate the at least one upper active layer from the source and drain regions; and
replacing the dummy gate with a replacement gate.

2. The method of claim 1 , wherein the active layers comprise a first material and the sacrificial layers comprise a second material, and wherein the first material is etchable selective to the second material.

3. The method of claim 2 , wherein the first material and the second material are each selected from the group consisting of: silicon, silicon germanium, III-V materials, and II-VI materials.

4. The method of claim 1 , further comprising the step of:
patterning each of the sacrificial and active layers in the at least one nano device stack beneath the at least one upper active layer to remove all but a portion of each of the sacrificial and active layers in the at least one nano device stack beneath the at least one upper active layer covered by the dummy gate and the spacers.

5. The method of claim 1 , wherein the spacers comprise a first set of spacers, the method further comprising the steps of:
recessing the sacrificial layers in the at least one nano device stack prior to forming the source and drain regions; and
forming a second set of spacers in gaps left by recessing the sacrificial layers,
wherein the replacement gate is separated from the source and drain regions by both the first set of spacers and the second set of spacers.

6. The method of claim 5 , wherein the first set of spacers comprises a different material from the second set of spacers.

7. The method of claim 1 , further comprising the step of:
removing the sacrificial layers selective to the active layers from the at least one nano device stack such that the replacement gate surrounds at least a portion of each of the active layers in a gate-all-around configuration.

8. A method of forming a semiconductor device, comprising the steps of:
forming an alternating series of sacrificial and active layers on a wafer;
patterning the sacrificial and active layers into multiple nano device stacks;
forming dummy gates on each of the nano device stacks;
forming a mask that selectively covers at least a second one of the nano device stacks, leaving at least one first nano device stack uncovered;
patterning at least one upper active layer in the at least one first nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gates on the at least one first device stack;
removing the mask after the at least one upper active layer has been patterned;
forming spacers on opposite sides of the dummy gates, wherein the spacers cover the at least one upper active layer that has been patterned in the at least one first nano device stack;
forming source and drain regions on opposite sides of the nano device stacks, wherein the at least one upper active layer is separated from the source and drain regions by the spacers in the at least one first nano device stack whereby the spacers electrically insulate the at least one upper active layer from the source and drain regions in the at least one first nano device stack; and
replacing the dummy gates with replacement gates.

9. The method of claim 8 , wherein the active layers comprise a first material and the sacrificial layers comprise a second material, and wherein the first material is etchable selective to the second material.

10. The method of claim 9 , wherein the first material and the second material are each selected from the group consisting of: silicon, silicon germanium, III-V materials, and II-VI materials.

11. The method of claim 8 , further comprising the step of:
patterning each of the sacrificial and active layers beneath the at least one upper active layer in the at least one first nano device stack to remove all but a portion of each of the sacrificial and active layers in the at least one first nano device stack beneath the at least one upper active layer covered by the dummy gates and the spacers.

12. The method of claim 8 , wherein the spacers comprise a first set of spacers, the method further comprising the steps of:
recessing the sacrificial layers in the nano device stacks prior to forming the source and drain regions; and
forming a second set of spacers in gaps left by recessing the sacrificial layers,
wherein the replacement gates are separated from the source and drain regions by both the first set of spacers and the second set of spacers.

13. The method of claim 12 , wherein the first set of spacers comprises a different material from the second set of spacers.

14. The method of claim 8 , further comprising the step of:
removing the sacrificial layers selective to the active layers from the nano device stacks such that the replacement gates surround at least a portion of each of the active layers in a gate-all-around configuration.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Miao Xin
• Xie Ruilong
• Yamashita Tenko

Classifications

• H01L29/78696 Primary

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/66742

  Electricity · mapped topic

• H01L29/78618

  Electricity · mapped topic