Ion trap array for high throughput charge detection mass spectrometry

Patent metadata

Field	Value
Publication number	US-11227759-B2
Application number	US-201917058561-A
Country	US
Kind code	B2
Filing date	Jan 11, 2019
Priority date	Jun 4, 2018
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

An electrostatic linear ion trap (ELIT) array includes multiple elongated charge detection cylinders arranged end-to-end and each defining an axial passageway extending centrally therethrough, a plurality of ion mirror structures each defining a pair of axially aligned cavities and an axial passageway extending centrally therethrough, wherein a different ion mirror structure is disposed between opposing ends of each cylinder, and front and rear ion mirrors each defining at least one cavity and an axial passageway extending centrally therethrough, the front ion mirror positioned at one end of the arrangement of charge detection cylinders and the rear ion mirror positioned at an opposite end of the arrangement of charge detection cylinders, wherein the axial passageways of the charge detection cylinders, the ion mirror structures, the front ion mirror and the rear ion mirror are coaxial to define a longitudinal axis passing centrally through the ELIT array. In a second aspect, an ELIT array comprises a plurality of non-coaxial ELIT regions, wherein ions are selectively guided into each of the ELIT regions.

First claim

What is claimed is:

1. An electrostatic linear ion trap (ELIT) array, comprising:
a plurality of elongated charge detection cylinders arranged end-to-end and each defining an axial passageway extending centrally therethrough,
a plurality of ion mirror structures each defining a pair of axially aligned cavities and each defining an axial passageway therethrough extending centrally through both cavities, wherein a different one of the plurality of ion mirror structures is disposed between opposing ends of each arranged pair of the elongated detection cylinders, and
front and rear ion mirrors each defining at least one cavity and an axial passageway extending centrally therethrough, the front ion mirror positioned at one end of the plurality of charge detection cylinders and the rear ion mirror positioned at an opposite end of the plurality of charge detection cylinders,
wherein the axial passageways of the plurality of charge detection cylinders, the plurality of ion mirror structures, the front ion mirror and the rear ion mirror are axially aligned with one another to define a longitudinal axis passing centrally through the ELIT array.

2. The ELIT array of claim 1 , wherein each of the plurality of ion mirror structures comprise a single ion mirror defining a single cavity, a first aperture at one end of the ion mirror open to the single cavity, a second aperture at an opposite end of the ion mirror and open to the single cavity, and a plate or ring positioned centrally with the single cavity and axially bisecting the single cavity into the pair of axially aligned cavities, the plate or ring defining a third aperture therethrough and open to both of the axially aligned cavities,
and wherein the longitudinal axis of the ELIT array extends centrally through first aperture, the second aperture, third aperture and the pair of axially aligned cavities of each of the plurality of ion mirror structures.

3. The ELIT array of any of claim 1 , wherein the front ion mirror defines a single cavity, a first aperture at one end of the front ion mirror open to the single cavity of the front ion mirror and a second aperture at an opposite end of the front ion mirror and open to the single cavity of the front ion mirror,
and wherein the longitudinal axis of the ELIT array extends centrally through the first and second apertures and through the single cavity of the front ion mirror,
and wherein the first aperture of the front ion mirror defines an ion inlet to the ELIT array and the second aperture of the front ion mirror is positioned opposite to an exposed end of the one of the plurality of charge detection cylinders at the one end of the plurality of charge detection cylinders.

4. The ELIT array of claim 1 , wherein the rear ion mirror defines a single cavity, a first aperture at one end of the rear ion mirror open to the single cavity of the rear ion mirror and a second aperture at an opposite end of the rear ion mirror and open to the single cavity of the rear ion mirror,
and wherein the longitudinal axis of the ELIT array extends centrally through first and second apertures and through single cavity of the rear ion mirror,
and wherein the first aperture of the rear ion mirror is positioned opposite to an exposed end of the one of the plurality of charge detection cylinders at the opposite end of the plurality of charge detection cylinders and the second aperture of the rear ion mirror defines an ion outlet of the ELIT array.

5. The ELIT array of claim 1 , further comprising at least one voltage source operatively coupled to each of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures and configured to produce voltages for selectively establishing an ion transmission electric field or an ion reflection electric field therein, the ion transmission electric field configured to focus an ion passing through a respective one of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures toward the longitudinal axis and the ion reflection electric field configured to cause an ion entering a respective one of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures from a respective one of the plurality of charge detection cylinders to stop and accelerate in an opposite direction back through the respective one of the plurality of charge detection cylinders while also focusing the ion toward the longitudinal axis.

6. The ELIT array of claim 5 , further comprising:
a processor operatively coupled to the at least one voltage source, and
a memory having instructions stored therein which, when executed by the processor, cause the processor to control the at least one voltage source to establish an ion transmission field with the cavities of each of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures such that ions entering the front ion mirror pass through each of the front ion mirror, the rear ion mirror, each of the plurality of ion mirror structures and each of the plurality of charge detection cylinders and exit the ELIT array.

7. The ELIT array of claim 6 , wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to control the at least one voltage source to establish the ion reflection field with the at least one cavity of the rear ion mirror while maintaining the ion transmission electric field in the cavities of the front ion mirror and the plurality of ion mirror structures.

8. The ELIT array of claim 7 , wherein the ELIT defines a plurality of axially aligned ELIT regions each including a different one of the plurality of charge detection cylinders and cavities of respective ones of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures positioned at opposite ends thereof,
and wherein the instructions stored in the memory further include instructions which, when executed by the processor, cause the processor to control the at least one voltage source to sequentially establish the ion reflection field with the cavities each of the plurality of ion mirror structures, beginning with the one of the plurality of ion mirror structures positioned at the opposite end of the one of the plurality of cylinders disposed between the rear ion mirror and the one of the plurality of ion mirror structures, while maintaining the ion transmission electric field in the cavities of the front ion mirror and each of the remaining plurality of ion mirror structures, followed by controlling the at least one voltage source to establish the ion reflection field with the at least one cavity of the front ion mirror, in a manner which successively traps a different one of the ions entering the front ion mirror in each of the plurality of ELIT regions such that an ion trapped within each of the plurality of ELIT regions oscillates back and forth between the cavities of the respective ones of the front ion mirror, the rear ion mirror and the plurality of ion mirror structures each time passing through a respective one of the plurality of charge detection cylinders.

9. The ELIT array of claim 8 , further comprising a plurality of charge preamplifiers each having an input operatively coupled to a different one of the plurality of charge detection cylinders and each having an output operatively coupled to the processor, each of the plurality of charge preamplifiers configured to produce charge detection signals upon detection of a charge induced on the respective one of the plurality of charge detection cylinders as a respective ion passes therethrough,
and wherein the instructions stored in the memory further include instructions which, when executed by the processor

Assignees

• Univ Indiana Trustees

Inventors

• Jarrold Martin F
• Botamanenko Daniel

Classifications

• H01J49/4245 Primary

  Electrostatic ion traps (H01J49/422 takes precedence) · CPC title

• H01J49/0031

  Step by step routines describing the use of the apparatus (H01J49/0081 takes precedence) · CPC title

• H01J49/025

  Detectors specially adapted to particle spectrometers (data acquisition H01J49/0036; detectors per se G01T, e.g. G01T1/28, G01T1/29) · CPC title

• H01J49/0036

  Step by step routines describing the handling of the data generated during a measurement · CPC title

• H01J49/022

  Circuit arrangements, e.g. for generating deviation currents or voltages (regulating electric or magnetic variables in general, e.g. current, magnetic field G05F); Components associated with high voltage supply (high voltage supply per se H02M) · CPC title