Filtering memory calibration

Patent metadata

Field	Value
Publication number	US-11226752-B2
Application number	US-201916293398-A
Country	US
Kind code	B2
Filing date	Mar 5, 2019
Priority date	Mar 5, 2019
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

Systems, methods and mechanisms for efficiently calibrating memory signals. In various embodiments, a computing system includes at least one processor, a memory and a power manager. The power manager generates and sends updated power-performance states (p-states) to the processor and the memory. Logic within a memory controller for the memory initializes a first timer corresponding to a first p-state of the multiple p-states to indicate a duration for skipping memory calibration. The logic continues to update the first timer while transferring data with the memory using operating parameters of the first p-state. When the memory is not using operating parameters of the first p-state, the logic prevents updates of the first timer. When the power manager determines to transition the memory from the first p-state to a second p-state, and the second timer for the second e-state has not expired, the logic prevents calibration of the memory.

First claim

What is claimed is:

1. An apparatus comprising:
a timer corresponding to a first power-performance state (p-state) of a plurality of p-states of a memory; and
circuitry configured to:
transfer data with the memory while the memory is operating in a second e-state different from the first p-state; and
responsive to receipt of a first indication to transition the memory from the second p-state to the first p-state:
inspect the timer; and
prevent calibration of the memory based at least in part on making
a determination that the timer has not expired after inspecting the timer.

2. The apparatus as recited in claim 1 , wherein in based at least in part on a determination that calibration of the memory is prevented, the circuitry is further configured to convey a second indication to one or more agents that a latency for the transition to the first p-state does not include an added latency for memory calibration.

3. The apparatus as recited in claim 1 , wherein the circuitry is further configured to prevent calibration of the memory based at least in part on:
receipt of an indication specifying to transition the memory to using operating parameters of the first p-state; and
a determination that:
the timer has expired, upon inspection of the timer responsive to receipt of the indication; and
another transition to another p-state will occur within a threshold amount of time.

4. The apparatus as recited in claim 1 , wherein the circuitry is further configured to permit calibration of the memory based at least in part on:
receipt of an indication to transition the memory to using operating parameters of the first p-state; and
a determination that the timer has expired, upon inspection of the timer responsive to receipt of the indication.

5. The apparatus as recited in claim 4 , wherein based at least in part on a determination that the calibration of the memory has completed, the circuitry is further configured to initialize the timer to indicate a duration during which memory calibration is not to be performed.

6. The apparatus as recited in claim 5 , wherein the circuitry is further configured to update the timer while transferring data with the memory using operating parameters of the first p-state.

7. The apparatus as recited in claim 5 , wherein in response to receiving an indication to transition the memory to using operating parameters of another p-state different from the first p-sate, the circuitry is further configured to prevent updating the first timer.

8. The apparatus as recited in claim 5 , wherein the apparatus further comprises a respective timer for each of the plurality of p-states.

9. A method, comprising:
maintaining, by circuitry in a memory controller, a first timer corresponding to a first power-performance state (p-state) of a plurality of p-states of a memory;
receiving, by the circuitry, memory requests from one or more agents;
transferring, by the circuitry, data with the memory while the memory is operating in a second p-state different from the first p-state; and
in response to receiving, by the circuitry, a first indication to transition the memory from the second p-state to the first p-state:
inspecting, by the circuitry, the timer; and
preventing, by the circuitry, calibration of the memory based at least in part on making a determination that the timer has not expired after inspecting the timer.

10. The method as recited in claim 9 , wherein in response to preventing calibration of the memory, the method further comprises conveying a second indication to the one or more agents that a latency for the transition to the first p-state does not include an added latency for memory calibration.

11. The method as recited in claim 9 , further comprising preventing calibration of the memory responsive to:
receiving an indication specifying to transition the memory to using operating parameters of the first p-state; and
determining:
the timer has expired, upon inspecting the timer responsive to receiving the first indication; and
another transition to another p-state will occur within a threshold amount of time.

12. The method as recited in claim 11 , wherein in response to determining the calibration of the memory has completed, the method further comprises initializing the timer to indicate a duration during which memory calibration is not to be performed.

13. The method as recited in claim 12 , further comprising updating the timer while transferring data with the memory using operating parameters of the first p-state.

14. The method as recited in claim 12 , wherein in response to receiving an indication to transition the memory to using operating parameters of another p-state different from the first p-sate, the method further comprises preventing updating the timer.

15. The method as recited in claim 12 , further comprising maintaining a respective timer for each of the plurality of p-states.

16. A computing system comprising:
one or more agents, each configured to generate memory requests;
a memory controller;
a memory configured to store data requested by the one or more agents;
a power manager configured to send updated power-performance states (p-states) to the one or more agents and the memory; and
wherein the memory controller is configured to:
maintain a timer corresponding to a first p-state of a plurality of p-states of the memory;
receive memory requests from the one or more agents;
transfer data with the memory while the memory is operating in a second e-state different from the first p-state; and
responsive to receipt of a first indication to transition the memory from the second p-state to the first p-state:
inspect the timer; and
prevent calibration of the memory based at least in part on making a determination that the timer has not expired after inspecting the timer.

17. The computing system as recited in claim 16 , wherein in response to preventing calibration of the memory, the memory controller is further configured to convey a second indication to one or more agents that a latency for the transition to the first p-state does not include an added latency for memory calibration.

18. The computing system as recited in claim 16 , wherein the memory controller is further configured to prevent calibration of the memory responsive to:
receiving an indication specifying to transition the memory to using operating parameters of the first p-state; and
determining:
the timer has expired, upon inspecting the timer responsive to receiving the first indication; and
another transition to another p-state will occur within a threshold amount of time.

19. The computing system as recited in claim 18 , wherein in response to determining the calibration of the memory has completed, the memory controller is further configured to initialize the timer to indicate a duration during which memory calibration is not to be performed.

20. The computing system as recited in claim 18 , wherein the memory controller is further configured to update the timer while transferring data with the memory using operating parameters of the first p-state.

Assignees

• Apple Inc

Inventors

• Notani Rakesh L
• Jeter Robert E
• Suvarna Ramesh Suhas Kumar
• Korada Naveen Kumar
• Rizwan Mohammad
• Juarez Dominguez Alma L
• Kelm John H
• Johnson Matthew R

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4072 Primary

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C2207/2254

  Calibration · CPC title