Array substrate for reducing parasitic capacitance between adjacent wires, display panel, and display device

Patent metadata

Field	Value
Publication number	US-11226528-B2
Application number	US-202016857979-A
Country	US
Kind code	B2
Filing date	Apr 24, 2020
Priority date	Jan 11, 2020
Publication date	Jan 18, 2022
Grant date	Jan 18, 2022

Abstract

An array substrate carrying a display area and a camera area surrounded by the display area provides connections to both areas free of electrical interference. The camera area includes a transparent area and a routing area surrounding the transparent area. The array substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes first wires and first capacitance compensation patterns. The second conductive layer includes second wires. Each first capacitance compensation pattern is between adjacent first wires. Along a thickness direction of the array substrate, a projection of each first capacitance compensation pattern on the substrate overlaps with a projection of at least one second wire. A display panel and a display device are also disclosed.

First claim

What is claimed is:

1. An array substrate defining a display area and a camera area surrounded by the display area, the camera area defining a transparent area and a routing area surrounding the transparent area, the array substrate comprising:
a substrate;
a first conductive layer on the substrate, the first conductive layer comprising a plurality of first wires around the transparent area;
an insulating layer on the first conductive layer, the insulating layer being electrically insulative;
a second conductive layer on the insulating layer, the second conductive layer comprising a plurality of second wires around the transparent area;
wherein the first conductive layer further comprises a plurality of first capacitance compensation patterns electrically insulated and spaced from the plurality of first wires;
each of the plurality of first capacitance compensation patterns is between adjacent first wires; and
a projection of each of the plurality of first capacitance compensation patterns on the substrate overlaps with a projection of at least one of the plurality of second wires along a thickness direction of the array substrate;
wherein the second conductive layer further comprises a plurality of second capacitance compensation patterns electrically insulated and spaced from the plurality of second wires;
each of the plurality of second capacitance compensation patterns is between adjacent second wires; and
a projection of each of the plurality of second capacitance compensation patterns on the substrate overlaps with a projection of at least one of the plurality of first wires along the thickness direction of the array substrate.

2. The array substrate according to claim 1 , wherein the plurality of first wires comprises a plurality of first scan lines;
each of the plurality of first scan lines bypasses the transparent area, crosses the routing area, and extends in a first direction in the display area; and
at least one of the plurality of first capacitance compensation patterns is arranged between adjacent first scan lines.

3. The array substrate according to claim 2 , wherein the plurality of second wires comprises a plurality of first data lines;
each of the plurality of first data lines bypasses the transparent area, crosses the routing area, and extends in a second direction in the display area;
the second direction intersects with the first direction; and
at least one of the plurality of second capacitance compensation patterns is between adjacent first data lines.

4. The array substrate according to claim 3 , further comprising a plurality of second data lines, wherein each of the plurality of second data lines bypasses the transparent area, crosses the routing area, and extends in the second direction in the display area;
each of the plurality of second data lines is alternatively arranged with one of the plurality of first data lines in the first direction;
the plurality of first wires further comprises a plurality of auxiliary data lines in the routing area;
the plurality of second wires further comprises a plurality of data line leads extending in the second direction in the routing area and the display area;
each of the plurality of auxiliary data lines is electrically coupled to one of the plurality of data line leads; and
each of the plurality of second data lines comprises one of the plurality of auxiliary data lines and one of the plurality of data line leads.

5. The array substrate according to claim 4 , wherein at least one of the plurality of first capacitance compensation patterns is between adjacent auxiliary data lines.

6. The array substrate according to claim 5 , wherein at least one of the plurality of second capacitance compensation patterns is between a pair of one of the plurality of first data lines and one of the plurality of second data lines adjacent to each other.

7. The array substrate according to claim 6 , wherein the plurality of second wires further comprises a plurality of third data lines;
each of the plurality of third data lines bypasses the transparent area, crosses the routing area, and extends in the second direction in the display area;
in the first direction, the plurality of third data lines is on a side of the plurality of first data lines and the plurality of second data lines away from the transparent area; and
at least one of the plurality of second capacitance compensation patterns is between adjacent third data lines.

8. A display panel, comprising:
a color filter substrate;
an array substrate; and
a liquid crystal layer between the color filter substrate and the array substrate, the array substrate defining a display area and a camera area surrounded by the display area, the camera area defining a transparent area and a routing area surrounding the transparent area, the array substrate comprising:
a substrate;
a first conductive layer on the substrate, the first conductive layer comprising a plurality of first wires around the transparent area;
an insulating layer on the first conductive layer, the insulating layer being electrically insulative;
a second conductive layer on the insulating layer, the second conductive layer comprising a plurality of second wires around the transparent area;
wherein the first conductive layer further comprises a plurality of first capacitance compensation patterns electrically insulated and spaced from the plurality of first wires; each of the plurality of first capacitance compensation patterns is between adjacent first wires; and a projection of each of the plurality of first capacitance compensation patterns on the substrate overlaps with a projection of at least one of the plurality of second wires along a thickness direction of the array substrate;
wherein the second conductive layer further comprises a plurality of second capacitance compensation patterns electrically insulated and spaced from the plurality of second wires;
each of the plurality of second capacitance compensation patterns is between adjacent second wires; and
a projection of each of the plurality of second capacitance compensation patterns on the substrate overlaps with a projection of at least one of the plurality of first wires along the thickness direction of the array substrate.

9. The display panel according to claim 8 , wherein the plurality of first wires comprises a plurality of first scan lines;
each of the plurality of first scan lines bypasses the transparent area, crosses the routing area, and extends in a first direction in the display area; and
at least one of the plurality of first capacitance compensation patterns is arranged between adjacent first scan lines.

10. The display panel according to claim 9 , wherein the plurality of second wires comprises a plurality of first data lines;
each of the plurality of first data lines bypasses the transparent area, crosses the routing area, and extends in a second direction in the display area;
the second direction intersects with the first direction; and
at least one of the plurality of second capacitance compensation patterns is between adjacent first data lines.

11. The display panel according to claim 10 , further comprising a plurality of second data lines, wherein each of the plurality of second data lines bypasses the transparent area, crosses the routing area, and extends in the second direction in the display area;
each of the plurality of second data lines is alternatively arranged with one of the plurality of first data lines in the first direction;
the plurality of first wires further comprises a plurality of auxiliary data lines in the routing area;
the plurality of second wires further comprises a plurality o

Assignees

• Hon Hai Prec Ind Co Ltd

Inventors

• Ouyang Shiang-Ruei
• Chen Wei-Cheng

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H04N23/57

  Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices · CPC title

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title