Edge interconnects for use with circuit boards and integrated circuits

Patent metadata

Field	Value
Publication number	US-11224126-B2
Application number	US-202016757880-A
Country	US
Kind code	B2
Filing date	Jan 9, 2020
Priority date	Jan 10, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A substrate assembly includes at least one printed circuit (PC) substrate. Each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface. The edge includes or defines on a facet or edge surface of the edge at least one projection that extends transverse or normal to the facet or edge surface. The projection includes a projection top surface and a projection bottom surface spaced from each other and the projection can include or be made of conductive material.

First claim

The invention claimed is:

1. A substrate assembly comprising:
at least one printed circuit (PC) substrate, wherein:
each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface;
the edge including or defining on a facet or edge surface of said edge at least one projection that extends transverse or normal to said facet or edge surface;
the projection including a projection top surface and a projection bottom surface spaced from each other; and
the projection comprises conductive material, wherein the at least one PC substrate includes a first PC substrate and a second PC substrate;
the projection of the first PC substrate includes its projection top surface coincident, coextensive, or residing in the same plane as its PC top surface and its projection bottom surface extending transverse from the facet or edge surface of the edge of the first PC substrate from a location between the PC top surface and the PC bottom surface of the first PC substrate;
the projection of the second PC substrate includes its projection bottom surface coincident, coextensive, or residing in the same plane as its PC bottom surface and its projection top surface extending transverse from the facet or edge surface of the edge of the second PC substrate from a location between the PC top surface and the PC bottom surface of the second PC substrate; and
the projection bottom surface of the first PC substrate overlaps and is in contact with the projection top surface of the second PC substrate.

2. The substrate assembly of claim 1 , wherein the conductive material includes a conductor formed on at least one of the projection top surface and the projection bottom surface.

3. The substrate assembly of claim 1 , wherein the projection is formed partially or entirely of the conductive material.

4. The substrate assembly of claim 1 , wherein:
the projection of the first PC substrate includes its conductive material on its projection bottom surface; and
the projection of the second PC substrate includes its conductive material on its projection top surface which makes electrical contact with the conductive material on the projection bottom surface of the projection of the first PC substrate when the projection bottom surface of the first PC substrate overlaps and is in contact with the projection top surface of the second PC substrate.

5. The substrate assembly of claim 1 , wherein the PC substrate is comprised of at least two layers.

6. A substrate assembly comprising:
at least one printed circuit (PC) substrate, wherein:
each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface;
the edge including or defining on a facet or edge surface of said edge at least one projection that extends transverse or normal to said facet or edge surface;
the projection including a projection top surface and a projection bottom surface spaced from each other; and
the projection comprises conductive material, wherein the projection includes at least one pair of projections having a recess therebetween, wherein each projection includes the projection top surface and the projection bottom surface coincident, coextensive, or residing in the same planes as the respective PC top surface and the PC bottom surface.

7. A substrate assembly comprising:
at least one printed circuit (PC) substrate, wherein:
each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface;
the edge including or defining on a facet or edge surface of said edge at least one projection that extends transverse or normal to said facet or edge surface;
the projection including a projection top surface and a projection bottom surface spaced from each other; and
the projection comprises conductive material, wherein the projection includes at least one pair of projections having a recess therebetween, wherein the at least one pair of projections includes:
a first pair of spaced projections in a first plane of the PC substrate having a first recess therebetween; and
a second pair of spaced projections in a second, parallel plane of the PC substrate having a second recess therebetween, wherein at least one of the first pair of projections is aligned, in a direction normal to the first and second planes, with the second recess, and at least one of the second pair of projections is aligned, in a direction normal to the first and second planes, with the first recess.

8. The substrate assembly of claim 7 , wherein:
the at least one PC substrate includes first and second PC substrates, each including the first and second pairs of spaced projections; and
the first and second PC substrates are positioned, arranged, or configured with the first and second pairs of spaced projections of the first PC substrate and the first and second pairs of spaced projections of the second PC substrate interdigitated with each other.

9. A substrate assembly comprising:
at least one printed circuit (PC) substrate, wherein:
each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface;
the edge including or defining on a facet or edge surface of said edge at least one projection that extends transverse or normal to said facet or edge surface;
the projection including a projection top surface and a projection bottom surface spaced from each other;
the projection comprises conductive material, wherein the projection is formed partially or entirely of the conductive material,
the at least one PC substrate includes first and second PC substrates, each including the projection made of the conductive material formed as a cantilevered beam having a proximal end supported by the PC substrate and a free, distal end, wherein a largest dimension of the conductive material formed as the cantilevered beam is a distance between the proximal end and the distal end; and
the first and second PC substrates are positioned, arranged, or configured adjacent or proximate each other with their respective projections in electrical contact, wherein one of the first and second PC substrates is a microchip or a rigid or flexible printed circuit board or printed wiring board and the other of the first and second PC substrates is a rigid or flexible printed circuit board or printed wiring board.

10. The substrate assembly of claim 9 , wherein:
the microchip is formed from a semiconductor material; and
each printed circuit board or printed wiring board is made from at least one of the following: a glass-reinforced epoxy laminate or a polyamide.

11. A substrate assembly comprising:
at least one printed circuit (PC) substrate, wherein:
each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface;
the edge including or defining on a facet or edge surface of said edge at least one projection that extends transverse or normal to said facet or edge surface;
the projection including a projection top surface and a projection bottom surface spaced from each other;
the projection comprises conductive material, wherein

Assignees

• Indiana Integrated Circuits Llc
• Science Appl Int Corp

Inventors

• Kulick Jason M
• Lu Tian
• Ortega Carlos J
• Engelhardt Jr Robert Joseph
• Timler John Philip

Classifications

• H05K2201/09845

  Stepped hole, via, edge, bump or conductor · CPC title

• H05K2201/0919

  Exposing inner circuit layers or metal planes at the side edge of the printed circuit board [PCB] or at the walls of large holes · CPC title

• H05K2201/09172

  Notches between edge pads · CPC title

• H05K3/36 Primary

  Assembling printed circuits with other printed circuits {(H05K7/142 takes precedence)} · CPC title

• H05K1/142

  Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit · CPC title