Re-purposing byte enables as clock enables for power savings

Patent metadata

Field	Value
Publication number	US-11223575-B2
Application number	US-201916725901-A
Country	US
Kind code	B2
Filing date	Dec 23, 2019
Priority date	Dec 23, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

First claim

What is claimed is:

1. A computing system, comprising:
a source comprising circuitry configured to generate a packet comprising:
a plurality of partitions of a data payload; and
a plurality of enable signals, each of the enable signals indicating whether an associated partition of the plurality of partitions includes valid data; and

a routing component comprising circuitry configured to:
receive the packet from the source; and
disable a clock signal for each storage element of a plurality of storage elements assigned to store data of a given partition of the plurality of partitions, in response to determining an enable signal corresponding to the given partition indicates the given partition does not store valid data.

2. The computing system as recited in claim 1 , wherein the routing component is further configured to convey to a destination:
the enable signal; and
a previous value stored in each storage element assigned to store data of the given partition.

3. The computing system as recited in claim 1 , wherein the routing component is further configured to enable a clock signal for each storage element of the routing component assigned to store data of the given partition, in response to:
determining the given partition has an associated enable signal in the packet that indicates the given partition stores valid data.

4. The computing system as recited in claim 1 , wherein the source is further configured to set the enable signal for the given partition to a value that indicates the given partition does not store valid data, in response to:
determining the given partition comprises a given data pattern.

5. The computing system as recited in claim 4 , wherein the packet is a response type of packet.

6. The computing system as recited in claim 4 , wherein the source is configured to:
insert an indication of the given data pattern in the given partition of the packet.

7. The computing system as recited in claim 1 , wherein the routing component further comprises one of a switch and a repeater of a communication fabric between the source and a destination.

8. The computing system as recited in claim 1 , wherein the source comprises one or more of a central processing unit, a graphics processing unit and a multimedia engine.

9. A method, comprising:
receiving, by a routing component, a packet comprising:
a plurality of partitions of a data payload; and
a plurality of enable signals, each of the enable signals indicating whether an associated partition of the plurality of partitions includes valid data;

disabling, by the routing component, a clock signal for each storage element of a plurality of storage elements assigned to store data of a given partition of the plurality of partitions, in response to determining an enable signal corresponding to the given partition indicates the given partition does not store valid data.

10. The method as recited in claim 9 , further comprising conveying to a destination:
the enable signal of the given partition; and
a previous value stored in each storage element assigned to store data of the given partition.

11. The method as recited in claim 9 , further comprising enabling a clock signal for each storage element of the routing component assigned to store data of the given partition, in response to:
determining the given partition has an associated enable signal that indicates the corresponding partition includes valid data.

12. The method as recited in claim 9 , further comprising setting an enable signal for the given partition to indicate the given partition does not include valid data, in response to:
determining the given partition comprises a given data pattern.

13. The method as recited in claim 12 , wherein the packet is a cache victim type of packet.

14. The method as recited in claim 12 , wherein the packet is a full size write type of packet.

15. The method as recited in claim 12 , further comprising:
inserting, by a source, an indication of the given data pattern in the given partition of the packet.

16. The method as recited in claim 9 , wherein the routing component comprises one of a switch and a repeater of a communication fabric between a source and a destination.

17. An apparatus, comprising:
a first interface configured to receive, from a source, a packet comprising:
a plurality of partitions of a data payload; and
a plurality of enable signals, each of the enable signals indicating whether an associated partition of the plurality of partitions includes valid data;

a second interface configured to convey the packet to a destination;
a plurality of storage elements; and
circuitry configured to disable a clock signal for each storage element of the plurality of storage elements assigned to store data of a given partition of the plurality of partitions, in response to determining an enable signal corresponding to the given partition indicates the given partition does not store valid data.

18. The apparatus as recited in claim 17 , wherein the circuitry is further configured to convey, via the second interface, to the destination:
the enable signal; and
a previous value stored in each storage element assigned to store data of the given partition.

19. The apparatus as recited in claim 17 , wherein the circuitry is further configured to enable a clock signal for each storage element of the plurality of storage elements assigned to store data of the given partition, in response to:
determining the given partition has an associated enable signal in the packet that indicates the given partition stores valid data.

20. The apparatus as recited in claim 17 , wherein the apparatus comprises a switch of a communication fabric between the source and the destination.

Assignees

• Advanced Micro Devices Inc

Inventors

• Donley Greggory D
• Kalyanasundharam Vydhyanathan
• Silla Mark A
• Chincholi Ashwin

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H04Q3/68

  Grouping or interlacing selector groups or stages · CPC title

• H04L69/22

  Parsing or analysis of headers · CPC title

• H04L67/1097

  for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS] · CPC title

• H04L49/356

  for storage area networks · CPC title