Receiver circuit performing adaptive equalization and system including the same

Patent metadata

Field	Value
Publication number	US-11223468-B1
Application number	US-202117194831-A
Country	US
Kind code	B1
Filing date	Mar 8, 2021
Priority date	Aug 18, 2020
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.

First claim

What is claimed is:

1. A receiver circuit, comprising:
an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient;
a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and
an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits, wherein:
the equalization control circuit generates a plurality of equalization state values by comparing, bit by bit, the plurality of data bits and the plurality of edge bits, and generates a state accumulation value by accumulating the equalization state values during an accumulation time interval, and
the equalization control circuit increases the state accumulation value when each data bit and each edge bit that are compared have equal values, and decreases the state accumulation value when each data bit and each edge bit that are compared have different values.

2. The receiver circuit as claimed in claim 1 , wherein the equalization control circuit determines an equalization state of the equalizer by comparing each data bit of the plurality of data bits with each edge bit of the plurality of edge bits, each edge bit being sampled later than each corresponding data bit.

3. The receiver circuit as claimed in claim 2 , wherein the equalization control circuit determines the equalization state of the equalizer by comparing each data bit of the plurality of data bits with each edge bit of the plurality of edge bits, each edge bit being sampled one and a half of a unit interval later than each corresponding data bit, the unit interval indicating a time interval between two adjacent data bits of the input data signal.

4. The receiver circuit as claimed in claim 1 , wherein the equalization control circuit generates each equalization state value of 1 when each data bit and each edge bit that are compared have equal values, and generates each equalization state value of 0 when each data bit and each edge bit that are compared have different values.

5. The receiver circuit as claimed in claim 1 , wherein the equalization control circuit includes at least one XOR gate configured to perform an XOR logic operation, bit by bit, on the plurality of data bits and the plurality of edge bits to output the plurality of equalization state values.

6. The receiver circuit as claimed in claim 1 , wherein the equalization control circuit determines that the equalizer is in an under-equalized state when the state accumulation value is greater than a first reference value, and determines that the equalizer is in an over-equalized state when the state accumulation value is smaller than a second reference value.

7. The receiver circuit as claimed in claim 6 , wherein the equalization control circuit increases the equalization coefficient to increase equalization strength of the equalizer when it is determined that the equalizer is in the under-equalized state, and decreases the equalization coefficient to decrease the equalization strength of the equalizer when it is determined that the equalizer is in the over-equalized state.

8. The receiver circuit as claimed in claim 1 , wherein the equalization control circuit generates a plurality of state accumulation values corresponding to a plurality of accumulation time intervals, and controls the equalization coefficient based on the plurality of state accumulation values until the equalization coefficient converges to a predetermined value.

9. The receiver circuit as claimed in claim 1 , wherein:
the clock data recovery circuit generates a plurality of parallel data sample signals by deserializing the data sample signal, and generates a plurality of parallel edge sample signals by deserializing the edge sample signal, and
the equalization control circuit controls the equalization coefficient by comparing data bits of an n-th parallel data sample signal of the plurality of parallel data sample signals and edge bits of an (n+1)-th parallel edge sample signal of the plurality of parallel edge sample signals, where n is a natural number.

10. The receiver circuit as claimed in claim 1 , wherein the clock data recovery circuit includes:
a data sampler configured to generate the data sample signal including the plurality of data bits by sampling the equalization signal in synchronization with the data clock signal;
an edge sampler configured to generate the edge sample signal including the plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and
a clock recovery circuit configured to generate the data clock signal and the edge clock signal based on the data sample signal and the edge sample signal.

11. The receiver circuit as claimed in claim 10 , wherein the clock data recovery circuit further includes:
a first deserializer configured to generate a plurality of parallel data sample signals by deserializing the data sample signal; and
a second deserializer configured to generate a plurality of parallel edge sample signals by deserializing the edge sample signal.

12. The receiver circuit as claimed in claim 1 , wherein the equalization control circuit includes:
a state monitor configured to generate the plurality of equalization state values by comparing, bit by bit, the plurality of data bits and the plurality of edge bits;
an accumulator configured to generate the state accumulation value by accumulating the equalization state values during the accumulation time interval; and
a control logic configured to control the equalization coefficient based on the state accumulation value.

13. The receiver circuit as claimed in claim 12 , wherein:
the state monitor includes:
a delay circuit configured to generate a delayed data sample signal by delaying the data sample signal;
an XOR gate configured to perform an XOR logic operation on the delayed data sample signal and the edge sample signal; and
a flip-flop configured to generate a state monitoring signal including the plurality of equalization state values by latching an output of the XOR gate, and

the accumulator includes a counter configured to generate the state accumulation value by increasing a stored value in the counter when each equalization state value is 1, and decreasing the stored value in the counter when each equalization state value is 0.

14. The receiver circuit as claimed in claim 12 , wherein:
the state monitor includes:
a delay circuit configured to generate a delayed data sample signal by delaying the data sample signal;
an XOR gate configured to perform an XOR logic operation on the delayed data sample signal and the edge sample signal;
an XNOR gate configured to perform an XNOR logic operation on the delayed data sample signal and the edge sample signal;
a first flip-flop configured to generate a first state monitoring signal by latching an output of the XOR gate; and
a second flip-flop configured to generate a second state monitoring signal by latching an output of the XNOR gate, and

the accumulator includes:
a first counter configured to increase a first stored value in the first counter when each bit value in the first state monitoring signal is 1;
a second c

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ryu Kyungho
• Kim Kyongho
• LEE Kilhoon
• Rhee Yeongcheol
• Lee Taeho
• Lim Hyunwook
• Chang Younghwan
• Chun Sengsub

Classifications

• H04L25/03082 Primary

  Theoretical aspects of adaptive time domain methods · CPC title

• H04J3/0638

  Clock or time synchronisation among nodes; Internode synchronisation (synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43) · CPC title

• H04B3/04

  Control of transmission; Equalising · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L2025/03681

  Control of adaptation · CPC title