Semiconductor structures including liners comprising alucone and related methods

US11223014B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11223014-B2
Application numberUS-201916446746-A
CountryUS
Kind codeB2
Filing dateJun 20, 2019
Priority dateFeb 25, 2014
Publication dateJan 11, 2022
Grant dateJan 11, 2022

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: stack structures overlying a material; and a liner on sidewalls of the stack structures, the liner comprising: a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures; and a second portion comprising alucone contacting the first portion, the second portion further comprising at least one of silicon atoms or nitrogen atoms. 2. The semiconductor device of claim 1 , wherein the liner comprises a gradient of alucone and aluminum oxide. 3. The semiconductor device of claim 1 , wherein the second portion comprises from about 10 atomic percent to about 20 atomic percent silicon. 4. The semiconductor device of claim 1 , wherein the liner comprises a ratio of aluminum oxide to alucone of from about 1:1 to about 1:10. 5. The semiconductor device of claim 1 , wherein the stack structures comprise an electrode and a switching material adjacent the electrode. 6. The semiconductor device of claim 1 , wherein the liner further comprises a third portion between the first portion and the second portion, the third portion comprising a greater amount of alucone than the first portion. 7. The semiconductor device of claim 1 , wherein the stack structures comprise an electrode between a switching material and a phase change material. 8. The semiconductor device of claim 1 , wherein the liner has a thickness ranging from about 5 Å to about 30 Å. 9. The semiconductor device of claim 1 , wherein the stack structures comprise alternating conductive materials and dielectric materials. 10. A semiconductor device, comprising: a base material; 3D-NAND memory structures comprising stack structures vertically overlying the base material, each stack structure comprising alternating dielectric materials and conductive materials, the alternating dielectric materials vertically spaced from each other by the conductive materials; and a liner comprising alucone on sidewalls of the stack structures, the liner comprising a gradient of aluminum oxide and alucone, a concentration of alucone increasing from about zero percent at the sidewalls of each stack structure to about one-hundred percent at an outer surface of the liner distal from the sidewalls of the respective stack structure. 11. The semiconductor device of claim 10 , wherein the stack structures comprises a control gate material. 12. The semiconductor device of claim 10 , wherein the liner has a thickness between about 5 Å and about 30 Å. 13. The semiconductor device of claim 10 , wherein the alternating dielectric materials comprise silicon dioxide. 14. The semiconductor device of claim 10 , wherein the alternating conductive materials comprise tungsten. 15. The semiconductor device of claim 10 , wherein the liner further comprises from about 10 atomic percent to about 20 atomic percent of at least one of silicon and nitrogen. 16. A method of forming a semiconductor device, the method comprising: forming stack structures overlying a base material; and forming a liner on sidewalls of the stack structures, forming the liner comprising: forming a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures; and forming a second portion comprising alucone contacting the first portion, the second portion further comprising at least one of silicon atoms and nitrogen atoms. 17. The method of claim 16 , wherein forming a second portion comprising alucone contacting the first portion comprises forming the second portion to exhibit a gradient of alucone and aluminum oxide. 18. The method of claim 16 , wherein forming stack structures overlying a base material comprises forming stack structures comprising alternating dielectric materials and conductive materials overlying the base material.

Assignees

Inventors

Classifications

  • characterised by the processes involved to create the masks · CPC title

  • the material containing aluminium, e.g. Al2O3 · CPC title

  • by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

  • deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

  • carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11223014B2 cover?
A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/69391. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 11 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).