Semiconductor device

Patent metadata

Field	Value
Publication number	US-11222973-B2
Application number	US-201616082212-A
Country	US
Kind code	B2
Filing date	Apr 11, 2016
Priority date	Apr 11, 2016
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a drift layer of a first conductivity type which is a wide-gap semiconductor layer provided on an upper surface of a semiconductor substrate of the first conductivity type;
a plurality of first well regions each of a second conductivity type provided, being separated from one another in a surface layer of the drift layer;
a first separation region of the first conductivity type provided penetrating from a surface layer of each of the first well regions in a depth direction;
a source region of the first conductivity type provided in the surface layer of each of the first well regions;
a first Schottky electrode provided on an upper surface of the first separation region;
a first ohmic electrode provided at least partially in a surface layer of the source region;
a second well region of the second conductivity type which is so provided in the surface layer of the drift layer as to sandwich the whole of the plurality of first well regions in a plan view and has an area larger than that of each of the first well regions;
a third well region of the second conductivity type which is so provided in the surface layer of the drift layer as to sandwich the second well region in a plan view and is also provided to overlap with a gate pad or a gate wire in a plan view and has an area larger than that of the second well region;
a second ohmic electrode provided in part of the second well region;
a dividing region of the first conductivity type provided between the second well region and the third well region; and
a source electrode connected to the first Schottky electrode, the first ohmic electrode, and the second ohmic electrode, wherein
the third well region has no electrical connection to the source electrode.

2. The semiconductor device according to claim 1 , further comprising:
a gate electrode provided on an upper surface of the first well region sandwiched between the source region and the drift layer, with a gate insulating film interposed therebetween,
wherein the gate electrode is provided also in a region corresponding to an upper surface of the third well region.

3. The semiconductor device according to claim 1 , wherein
a voltage V obtained from the following Eq. 1 is not higher than 50 V,

V
=

qNW
2

(

2
⁢
ɛ

)

(
1
)

where the width of the dividing region in a direction connecting the second well region and the third well region is W, the effective impurity concentration of the dividing region is N, the dielectric constant of semiconductor is ε, and the elementary electric charge is q.

4. The semiconductor device according to claim 1 , wherein the dividing region surrounds the second ohmic electrode in a plan view.

5. The semiconductor device according to claim 1 , further comprising:
a second separation region of the first conductivity type provided penetrating from a surface layer of the second well region in a depth direction; and
a second Schottky electrode provided on an upper surface of the second separation region.

6. The semiconductor device according to claim 2 , further comprising:
a field insulating film provided on at least part of the upper surface of the third well region, wherein
the thickness of the field insulating film is larger than that of the gate insulating film, and
the gate electrode is provided on the upper surface of the third well region, with the field insulating film interposed therebetween, in a region in which the field insulating film is provided.

7. The semiconductor device according to claim 6 , wherein the gate electrode is provided on the upper surface of the third well region, with the field insulating film interposed therebetween, in the region corresponding to the upper surface of the third well region.

8. The semiconductor device according to claim 1 , further comprising:
a well injection region of the second conductivity type provided in a surface layer of the third well region, wherein
the impurity concentration of the well injection region is higher than that of the first well region.

9. The semiconductor device according to claim 1 , further comprising:
at least one auxiliary conductive region of the second conductivity type provided in a surface layer of the dividing region, wherein
the auxiliary conductive region electrically connects the second well region and the third well region.

10. The semiconductor device according to claim 9 , wherein
a total length in which the auxiliary conductive region is provided is not larger than one tenth of a total length in which the dividing region is provided,
the length in which the auxiliary conductive region is provided is a length in which the auxiliary conductive region is provided in a direction intersecting a direction connecting the second well region and the third well region, and
the length in which the dividing region is provided is a length in which the dividing region is provided in a direction intersecting a direction connecting the second well region and the third well region.

11. The semiconductor device according to claim 1 , wherein a punch through current flows between the second well region and the third well region through the dividing region.

12. The semiconductor device according to claim 1 , wherein an upper surface of the dividing region is in contact with an insulator.

Assignees

• Mitsubishi Electric Corp

Inventors

• Hino Shiro
• Sadamatsu Koji
• Hatta Hideyuki
• NAGAHISA Yuichi
• Ebihara Kohei

Classifications

• H10D84/86

  of Schottky-barrier gate FETs · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/105

  by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  (IGFETs having LDD or drain extension regions H10D30/601) · CPC title