State table complexity reduction in a hierarchical verification flow

Patent metadata

Field	Value
Publication number	US-11222154-B2
Application number	US-202017063059-A
Country	US
Kind code	B2
Filing date	Oct 5, 2020
Priority date	Oct 10, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

State table complexity reduction in a hierarchical verification flow is provided by identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the power supplies provide outputs to or receive inputs from circuity external to the hierarchical group; merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group; removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and modeling a reduced logical block based on the reduced power state table.

First claim

What is claimed is:

1. A method, comprising:
identifying peripheral supplies and non-peripheral supplies in a hierarchical group in a hierarchical logical block model of a circuit based on whether logic blocks associated with the peripheral and non-peripheral supplies provide outputs to or receive inputs from circuity external to the hierarchical group;
merging associated power state tables for the peripheral supplies and the non-peripheral supplies in the hierarchical group to create a merged power state table for the hierarchical group;
removing, by a processing device, any power states associated with the non-peripheral supplies from the merged power state table to create a reduced power state table; and
modeling a reduced logical block based on the reduced power state table.

2. The method of claim 1 , further comprising:
identifying second peripheral supplies and second non-peripheral supplies in a next-higher hierarchical group that includes the hierarchical group in the hierarchical logical block model of the circuit, wherein the peripheral supplies are associated with the hierarchical group;
merging associated second power state tables for each of the second peripheral supplies and the second non-peripheral supplies in the next-higher hierarchical group to create a second merged power state table for the next-higher hierarchical group, wherein the reduced power state table is treated as one of the associated power state tables;
removing any power states associated with the second non-peripheral supplies from the second merged power state table to create a second reduced power state table; and
modeling a second reduced logical block based on the second reduced power state table.

3. The method of claim 1 , further comprising:
identifying second peripheral supplies and second non-peripheral supplies in a second hierarchical group in the hierarchical logical block model of the circuit at a shared hierarchical level with the hierarchical group;
merging associated power state tables for each of the second peripheral supplies and the second non-peripheral supplies in the second hierarchical group to create a second merged power state table for the second hierarchical group;
removing any power states associated with the second non-peripheral supplies from the second merged power state table to create a second reduced power state table; and
merging the reduced power state table with the second reduced power state table when modeling a next-higher hierarchical group that includes the hierarchical group and the second hierarchical group.

4. The method of claim 1 , wherein the non-peripheral supplies are associated with logic blocks in the hierarchical group that do not accept input from outside of the hierarchical group and that do not provide output outside to the hierarchical group.

5. The method of claim 1 , further comprising:
identifying unused and used power state for a peripheral supply; and
removing the unused power state from the reduced power state table.

6. The method of claim 1 , further comprising:
removing duplicate entries from the reduced power state table.

7. The method of claim 1 , wherein the power states associated with the non-peripheral supplies include a plurality of ON states and an OFF state.

8. A system, comprising:
a processor; and
a memory including instructions that when executed by the processor enable the processor to:
divide a circuit undergoing hierarchical verification flow into a plurality of hierarchical levels having a plurality of hierarchical groups;
identify which power supplies analyzed in the circuit in a first hierarchical level are peripheral supplies and which of the power supplies are non-peripheral supplies based on whether logic blocks associated with the power supplies receive inputs from or provide outputs to circuity external to the hierarchical groups;
merge, in each group at the first hierarchical level, power state tables for the power supplies within each individual group;
remove, in each group, power states associated with the non-peripheral supplies for each corresponding group to produce a corresponding reduced power state table for each individual group; and

in response to determining that the first hierarchical level is not a top hierarchical level for the circuit, output the corresponding reduced power table for each group in analyzing a next-higher hierarchal level of the circuit.

9. The system of claim 8 , wherein the instructions further enable the processor to:
identify which next-higher power supplies analyzed in the circuit in next-higher hierarchical level are next-higher peripheral supplies and which of the next-higher power supplies are next-higher non-peripheral supplies, wherein the peripheral supplies from the first hierarchical level are included in the next-higher power supplies;
merge, in each next-higher group at the next-higher hierarchical level, next-higher power state tables for all of the next-higher power supplies within each individual next-higher group; and
remove, in each next-higher group, next-higher power states associated with the next-higher non-peripheral supplies for each corresponding next-higher group to produce a corresponding next-higher reduced power state table for each individual next-higher group.

10. The system of claim 9 , wherein the instructions further enable the processor to:
in response to determining that the first hierarchical level is the top hierarchical level for the circuit, model the circuit based on the corresponding next-higher reduced power state table.

11. The system of claim 8 , wherein the instructions further enable the processor to:
remove unused power states for the peripheral supplies from the corresponding reduced power state table for each individual group.

12. The system of claim 8 , wherein the instructions further enable the processor to:
remove repeated power state combinations from the corresponding reduced power state table for each individual group.

13. The system of claim 8 , wherein the peripheral supplies are associated with peripheral logic blocks that are connected to at least one of an input and an output external to the groups, and wherein the non-peripheral supplies are associated with non-peripheral logic blocks that are not connected to any inputs or outputs external to the groups.

14. The system of claim 8 , wherein each of the peripheral supplies are associated with an OFF state and at least one ON state.

15. A non-transitory computer readable storage medium including instructions that when executed by a processor cause the processor to:
modeling a set of logic blocks as a simplified logic block comprising a first peripheral logic block, a second peripheral logic block, and a non-peripheral logic block;
identify a first power supply associated with the first peripheral logic block, a second power supply associated with the second peripheral logic block, and a third power supply associated with the non-peripheral logic block;
generate a first combined power state table for the first power supply and the second power supply;
generate a second combined power state table for the second power supply and the third power supply;
merge the first combined power state table and the second combined power state table with a constraint imposed by the second combined power state table to create a merged power state table;
remove power states for the third power supply from the merged power state table to produce a reduced power state table; and
remodel the set of logic blocks with the non-peripheral logic block and the third power supply remove

Assignees

• Synopsys Inc

Inventors

• De Kaushik
• Mukherjee Rajarshi
• Allen David L
• Pal Bhaskar
• Gulati Sanjay
• Pratap Gaurav
• Patel Nishant
• Kulatunga Malitha
• Bansal Sachin

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F30/3308 Primary

  using simulation · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title