System and method for power verification using efficient merging of power state tables

Patent metadata

Field	Value
Publication number	US-10311192-B2
Application number	US-201514815202-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Mar 30, 2015
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A power verification system requires a combination of design and its power intent. A power intent (PI) input specifies the power architecture of a design through specification of power/voltage domains, their corresponding power supplies and a collection of power management devices. Power state tables (PSTs) specified in PI capture the legal combinations of power states (voltage values) for the various sets of supply nets or supply ports of a design. A power verification system requires determining the power supply relationships of voltage/power domains which requires merging of PSTs. The system described efficiently merges PSTs by iteratively selecting only a subset of PSTs that are relevant to the supply pair of interest, that are pruned initially and as the merge progresses. This provides orders of magnitude speedup and resource reduction. A user interface allows display of identified power verification failures and may include an input device for facilitating correction of at least one of the electronic circuit design and the power intent file.

First claim

What is claimed is:

1. A method implemented for a power verification tool in a computing system for constructing power state tables in a verification of power implementation of an electronic circuit design, the method comprising:
receiving a description of at least a portion of an electronic circuit design having two or more power domains, and storing the received description in a storage medium accessible to a processor;
receiving and storing in the storage medium a power intent file that specifies a power architecture of power/voltage domains, their power supplies and corresponding power devices of the electronic circuit design, the power intent file comprising a plurality of power state tables that define allowed combinations of power states;
preparing, by the processor, to construct merged power state tables by removing power states from the power state tables in the power intent file,
comprising:
creating a scope tree representing a hierarchy of modules of the electronic circuit design with a root node being a top scope of the tree; and
at every scope, while traversing the scope tree in a child-first, parent-next post order traversal, (a) creating a list of power state tables, (b) for each pair of power state tables, removing any power states that are present in only one power state table, (c) whenever there is a power state table list at child scope, adding power state tables from that list to a consolidated power state table list used in step (b), and (d) saving the consolidated power state table list for that scope;

constructing, by the processor, merged power state tables for pairs of power supplies of interest by selectively merging those power state tables that establish a relationship between the two power supplies of interest in the pair; and
using the merged power state tables to verify whether the description of the electronic circuit design complies with the power intent file.

2. The method as in claim 1 , wherein the received description is provided in a register transfer level (RTL) format.

3. The method as in claim 1 , wherein the received description is provided as a netlist.

4. The method as in claim 1 , wherein the electronic circuit design corresponding to the received description comprises a plurality of modules of a system-on-chip circuit, each individual module having at least one power domain and at least two modules of the system-on-chip having different power domains.

5. The method as in claim 1 , wherein selectively merging power state tables comprises iteratively selecting pairs of power supplies of interest and for each power supply pair:
identifying whether the selected supply pair is related;
if unrelated, taking all possible combinations of port states of the selected supply pair used in their power state tables to build the merged power state table;
if related, identifying power state table lists for the related supply pair and merging the identified power state tables on the identified lists for the related supply pair;
merging identified power state tables two at a time, including removing any power supplies, other than the selected power supply pair, from the power state tables that are found in only one power state table, thereby maintaining a minimum size for the merged power state table; and
specifying, based on merged power supply tables, the relationship, if any, between the selected power supply pair.

6. The method as in claim 1 , further comprising:
displaying on a computer display identified power verification failures and using an input device to facilitate correction and storage of at least one of the electronic circuit design and the power intent file.

7. The method as in claim 1 , wherein selectively merging power state tables comprises, for pairs of power supplies of interest comprising a first power supply and a second power supply:
determining whether a first set of power supplies related to the first power supply overlaps with a second set of power supplies related to the second power supply, wherein power supplies in a power state table are defined to be directly related to each other and the set of power supplies related to a given power supply are those power supplies that are related to the given power supply either directly or indirectly;
if the first set of power supplies overlaps with the second set of power supplies, merging those power state tables that contain any of the power supplies in either the first or second sets of related power supplies to construct the merged power state table for the pair; and
if the first set of power supplies does not overlap with the second set of power supplies, using all possible combinations of port states of the first and second power supplies to construct the merged power state table.

8. The method as in claim 7 , wherein determining whether the first and second sets of power supplies overlap comprises:
creating a supply list for the first power supply, the supply list listing the power supplies that are related to the first power supply either directly or indirectly; and
determining whether the supply list contains the second power supply.

9. The method as in claim 8 , wherein creating the supply list for the first power supply comprises:
initially creating the supply list as containing the first power supply;
to a list of power state tables, adding any power state tables that contain any of the power supplies in the supply list and that are not already in the list of power state tables;
to the supply list, adding any power supplies that are from power state tables in the list of power state tables and that are not already in the supply list; and
repeating the steps of adding to the list of power state tables and adding to the supply list until either (a) the second power supply qualifies to be added to the supply list, or (b) no additional power supplies are added to the supply list.

10. A power verification system, comprising:
a storage medium for receiving and storing a description of at least a portion of an electronic circuit design having two or more power domains, and for receiving and storing a power intent file specifying a power architecture of power/voltage domains, their power supplies and corresponding power devices of the electronic circuit design, the power intent file comprising a plurality of power state tables that define allowed combinations of power states, and also for storing a report of power verification failures;
a processor having access to the storage medium and executing an application program for a power verification tool that constructs merged power state tables corresponding to the power domains of the electronic circuit design and that uses the merged power state tables to verify whether the electronic circuit design complies with the power intent file; and
a user interface including a computer display for displaying identified power verification failures and an input device for facilitating correction of at least one of the electronic circuit design and the power intent file;
wherein the processor executing the application program (a) prepares to construct merged power state tables by removing power states from the power state tables in the power intent file by creating a scope tree representing a hierarchy of modules of the electronic circuit design with a root node being a top scope of the tree and, at every scope, while traversing the scope tree in a child-first, parent-next post order traversal, (i) creating a list of power state tables, (ii) for each pair of power state tables, removing any power states that are present in only one power state table, (iii) whenever there is a power state table list at child scope, adding power state tables from that lis

Assignees

• Synopsys Inc

Inventors

• Venkatesh Shekaripuram V
• Gulati Sanjay
• Keswani Vishal
• Goel Manish
• Sharma Nitin

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F17/5081 Primary

  Physics · mapped topic