Allocation of buffer interfaces for moving data, and related systems, methods and devices

Patent metadata

Field	Value
Publication number	US-11221976-B2
Application number	US-201916258171-A
Country	US
Kind code	B2
Filing date	Jan 25, 2019
Priority date	Jan 25, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A buffer interface, data transport method, and computing system are described in which a buffer interface may be configured for communicating data samples to and from frame buffers defined in a memory. The configurable buffer interfaces and frame buffers provide a flexible and scalable platform for use with many applications.

First claim

What is claimed is:

1. A method of moving data to and from a memory, comprising:
determining processing frame parameters and data sampling parameters associated with active communication channels of an embedded system;
allocating regions of a memory as frame buffer regions, respective amounts of memory being allocated to frame buffer regions corresponding to quantities and widths of data samples specified by the processing frame parameters and the data sampling parameters;
configuring input line buffers for communication over an interconnect operatively coupling the input line buffers to the frame buffer regions;
moving data samples from the configured input line buffers to the allocated frame buffer regions at input locations pointed at by frame buffer input pointers;
detecting that a frame buffer of the allocated frame buffer regions is full; and
notifying a processing system that the moved data samples are available at the frame buffer responsive to the detecting.

2. The method of claim 1 , wherein allocating frame buffer regions of the memory comprises:
allocating at least two frame buffers, the at least two frame buffers comprising a first frame buffer and a second frame buffer;
associating the at least two frame buffers with respective different communication channels of the active communication channels; and
determining and storing the processing frame parameters for the at least two frame buffers.

3. The method of claim 2 , wherein determining and storing the processing frame parameters for the at least two frame buffers comprise:
calculating at least two processing frame durations, the at least two processing frame durations comprising a first processing frame duration and a second processing frame duration;
allocating a first frame buffer input pointer configured to point to the first frame buffer;
allocating a second frame buffer input pointer configured to point to the second frame buffer;
storing the first processing frame duration, first frame buffer input pointer, and a first sampling rate; and
storing the second processing frame duration, second frame buffer input pointer, and a second sampling rate.

4. The method of claim 3 , wherein calculating at least two processing frame durations comprises calculating the first processing frame duration responsive to a first sampling rate and a target number of samples, and calculating the second processing frame duration responsive to a second sampling rate and the target number of samples.

5. The method of claim 2 , further comprising processing the data samples moved to the frame buffer regions.

6. The method of claim 1 , wherein moving the data samples from the input line buffers to the frame buffer regions at input locations pointed at by the frame buffer input pointers comprises:
requesting write access to the input locations at the frame buffer regions;
providing the data samples and the input locations to the interconnect that operatively couples the line buffers to the frame buffer regions; and
receiving the data samples at the input locations at the frame buffer regions.

7. The method of claim 6 , wherein moving the data samples from the input line buffers to the frame buffer regions at input locations pointed at by the input pointers further comprises:
moving data samples from a first line buffer of the input line buffers to a first frame buffer of the allocated frame buffer regions; and
moving data samples from a second line buffer of the input line buffers to a second frame buffer of the allocated frame buffer regions.

8. The method of claim 1 , wherein detecting that at least one frame buffer of the frame buffer regions is full comprises:
incrementing a sample count responsive to moving data samples from a line buffer of the input line buffers to the at least one frame buffer; and
detecting that the sample count is equal to, or greater than, a pre-defined sample count.

9. The method of claim 1 , wherein allocating frame buffer regions of the memory comprises:
allocating two pairs of frame buffers, two pairs of frame buffers comprising a first pair of frame buffers and a second pair of frame buffers; and
determining and storing configuration parameters for the at least two pairs of frame buffers.

10. The method of claim 9 , further comprising, processing contents of one frame buffer of the first pair of frame buffers while moving data from the line buffers to the other frame buffer of the first pair of frame buffers.

11. The method of claim 9 , wherein determining and storing configuration parameters for the at least two pairs of frame buffers comprise:
calculating at least two processing frame durations, the at least two processing frame durations comprising a first processing frame duration and a second processing frame duration;
allocating a first pair of frame buffer input pointers configured to point to locations at the first pair of frame buffers;
allocating a second pair of frame buffer input pointers configured to point to locations at the second pair of frame buffers;
associating the first pair of frame buffers with a first pair of line buffers, the first processing frame duration, the first pair of frame buffer input pointers, and a first sampling rate; and
associating the second pair of frame buffers with a second pair of line buffers, the second processing frame duration, second pair of frame buffer input pointers, and a second sampling rate.

12. The method of claim 9 , wherein moving data samples from the input line buffers to the frame buffer regions at input locations pointed at by input pointers comprises:
moving data samples from the input line buffers to a frame buffer of the first pair of frame buffers at a location pointed at by the first pair of frame buffer input pointers;
pointing the first pair of frame buffer input pointers to point to a location at the other frame buffer of the first pair of frame buffers responsive to the frame buffer of the first pair of frame buffers being full; and
moving data samples from the input line buffers to the other frame buffer of the first pair of frame buffers at the location at the other frame buffer pointed at by the first pair of frame buffer input pointers.

13. The method of claim 12 , wherein calculating at least two processing frame durations comprises:
calculating the first processing frame duration responsive to a first sampling rate and a target number of samples, and calculating the second processing frame duration responsive to a second sampling rate and the target number of samples, and
wherein the first processing frame duration is for processing samples stored in the first pair of frame buffers, and the second processing frame duration is for processing samples stored in the second pair of frame buffers.

14. The method of claim 12 , wherein the configuring the line buffers for communication over the interconnect that operatively couples the line buffers to the frame buffer regions comprises configuring the line buffers to pack bits of data samples into bit locations of a data frame.

15. The method of claim 1 , further comprising:
configuring output line buffers for communication over one or more interconnects operatively coupled to the output line buffers;
moving processed data samples at output locations pointed at by output pointers from the frame buffer regions to the output line buffers; and
providing the processed data samples to the one or more interconnects.

16. A data samples processing system, comprising:
a memory; and
a processor comprising one or more processing cores, the processor configure

Assignees

• Microchip Tech Inc

Inventors

• Raj S V Narendra
• Gupta Priyank
• Simmons Michael

Classifications

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title