Nonvolatile memory module and storage system having the same

US2016357481A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016357481-A1
Application numberUS-201615132466-A
CountryUS
Kind codeA1
Filing dateApr 19, 2016
Priority dateJun 8, 2015
Publication dateDec 8, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data.

First claim

Opening claim text (preview).

What is claimed is: 1 . A nonvolatile memory module comprising: at least one nonvolatile memory; and a device controller including a random access memory (RAM) to store data exchanged between a host and the at least one nonvolatile memory, and a dual in-line memory module (DIMM) controller to control data exchanged between the RAM and the at least one nonvolatile memory; wherein an allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data. 2 . The nonvolatile memory module of claim 1 , wherein during a write operation regarding the nonvolatile memory module, an area is allocated by the host at which the data is to be stored when storing the data in the RAM, and the DIMM controller releases the allocation for the area, at which the data is stored, when reading the data from the RAM. 3 . The nonvolatile memory module of claim 1 , wherein during a read operation regarding the nonvolatile memory module, the DIMM controller allocates an area, at which the data is to be stored, when storing the data in the RAM, and the allocation for the area at which the data is stored is released by the host when reading the data from the RAM. 4 . The nonvolatile memory module of claim 1 , wherein the DIMM controller includes an area manager configured to generate status information indicating whether the DIMM controller reads the data stored in the RAM. 5 . The nonvolatile memory module of claim 4 , wherein the RAM includes a status area to store the status information. 6 . The nonvolatile memory module of claim 1 , wherein an overwrite operation regarding the allocated access area is inhibited and an overwrite operation about the released access area is permitted. 7 . The nonvolatile memory module of claim 1 , wherein at least one nonvolatile memory communicates with each the host through a dual data rate (DDR) interface. 8 . The nonvolatile memory module of claim 1 , wherein the at least one nonvolatile memory comprises a dual in-line memory module (DIMM). 9 . The nonvolatile memory module of claim 1 , wherein the at least one nonvolatile memory includes a three-dimensional memory array. 10 . A storage system, including: a host; and a nonvolatile memory module including at least one nonvolatile memory, a RAM to store data exchanged between the host and the at least one nonvolatile memory, and a device controller including a DIMM controller to control data exchanged between the RAM and the at least one nonvolatile memory; wherein an allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data. 11 . The nonvolatile memory module of claim 10 , wherein during a write operation regarding the nonvolatile memory module, the host allocates an area, at which the data is to be stored, when storing the data in the RAM and the DIMM controller releases the allocation for the area, at which the data is stored, when reading the data from the RAM. 12 . The nonvolatile memory module of claim 11 , wherein the DIMM controller includes a first area manager configured to generate status information indicating whether the DIMM controller reads the data stored in the RAM. 13 . The nonvolatile memory module of claim 10 , wherein during a read operation regarding the nonvolatile memory module, the DIMM controller allocates an area, at which the data is to be stored, when storing the data in the RAM and the host releases the allocation for the area, at which the data is stored, when reading the data from the RAM. 14 . The nonvolatile memory module of claim 13 , wherein the host includes a second area manager configured to generate status information indicating whether the host reads the data stored in the RAM. 15 . The nonvolatile memory module of claim 10 , wherein an overwrite operation about the allocated access area is inhibited and an overwrite operation about the released access area is permitted. 16 . A nonvolatile memory module to operate in association with a host, the nonvolatile memory module comprising: a plurality of nonvolatile memories defined by dual in-line memory modules (DIMM); a device controller including a random access memory (RAM) to store data exchanged between the host and the nonvolatile memories, and a DIMM controller to control data exchanged between the RAM and the at least one nonvolatile memory; wherein an allocation for an access area at an access to the RAM is performed during a write transaction in which data is recorded at the RAM and is released during a read transaction of the recorded data. 17 . The nonvolatile memory module of claim 16 , wherein during a write operation regarding the nonvolatile memory module, an area is allocated by the host at which the data is to be stored when storing the data in the RAM, and the DIMM controller releases the allocation for the area, at which the data is stored, when reading the data from the RAM. 18 . The nonvolatile memory module of claim 16 , wherein during a read operation regarding the nonvolatile memory module, the DIMM controller allocates an area, at which the data is to be stored, when storing the data in the RAM, and the allocation for the area at which the data is stored is released by the host when reading the data from the RAM. 19 . The nonvolatile memory module of claim 16 , wherein the DIMM controller includes an area manager configured to generate status information indicating whether the DIMM controller reads the data stored in the RAM. 20 . The nonvolatile memory module of claim 16 , wherein an overwrite operation regarding the allocated access area is inhibited and an overwrite operation about the released access area is permitted.

Assignees

Inventors

Classifications

  • G06F3/0647Primary

    Migration mechanisms · CPC title

  • Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • G06F3/0619Primary

    in relation to data integrity, e.g. data losses, bit errors · CPC title

  • Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

  • Non-volatile semiconductor memory arrays · CPC title

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What does patent US2016357481A1 cover?
The nonvolatile memory module includes at least one nonvolatile memory, and a device controller including a RAM to store data exchanged between a host and the at least one nonvolatile memory and a DIMM controller to control data exchange between the RAM and the at least one nonvolatile memory. An allocation for an access area at an access to the RAM is performed during a write transaction in wh…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/0647. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).