Sort and merge instruction for a general-purpose processor

Patent metadata

Field	Value
Publication number	US-11221850-B2
Application number	US-202017037962-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	Nov 6, 2018
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

First claim

What is claimed is:

1. A computer program product for facilitating processing within a computing environment, the computer program product comprising:
at least one computer readable storage medium readable by at least one processing circuit and storing instructions for performing a method comprising:
obtaining an instruction to perform a sort operation, the instruction being a single architected machine instruction of an instruction set architecture, and the instruction to access one field to be used to designate a location, the location to be used to store one or more output list delineations; and
executing, by a general-purpose processor of the computing environment, the instruction, the executing comprising:
sorting a plurality of input lists to obtain one or more sorted output lists; and
providing as output the one or more sorted output lists and providing the one or more output list delineations, the one or more output list delineations being based on the one or more sorted output lists, wherein an output list delineation of the one or more output list delineations corresponds to a sorted output list of the one or more sorted output lists and includes information relating to the sorted output list, the information including a length of the sorted output list.

2. The computer program product of claim 1 , wherein the instruction includes an operation code field including an operation code to specify a sort list operation, and has access to another field to be used to designate another location, the another location to be used in storing the one or more sorted output lists.

3. The computer program product of claim 2 , wherein the one field is a register field, the register field designating a register, the register including an address of the location, and the another field is another register field, the another register field designating another register, the another register including an address of the another location.

4. The computer program product of claim 1 , wherein the instruction employs one select register to determine a function to be performed by the instruction.

5. The computer program product of claim 4 , wherein the function is selected from a group of functions consisting of: a query available functions function, a sort fixed-length records function, and a sort variable-length records function.

6. The computer program product of claim 4 , wherein the instruction employs another select register to locate a parameter block in memory used by the instruction, the parameter block including information used by the instruction depending on the function to be performed.

7. The computer program product of claim 6 , wherein the function to be performed is a sort fixed-length records function or a sort variable-length records function, and the parameter block includes information to locate the plurality of input lists and information to continue the sorting, based on the sorting being interrupted.

8. The computer program product of claim 6 , wherein the one select register further comprises a mode of operation indicator, the mode of operation indicator to be used to specify whether a merge of the one or more sorted output lists is to be performed.

9. The computer program product of claim 6 , wherein the one select register is one implied register and the other select register is another implied register.

10. The computer program product of claim 1 , wherein the instruction includes an operation code field including an operation code to specify a sort list operation; one register field including a designation of one register, the one register including an address used in storing the one or more output list delineations; and another register field including a designation of another register, the another register including an address used in storing the one or more sorted output lists, and wherein the instruction employs a first implied register to determine a function to be performed by the instruction and a second implied register to locate a parameter block in memory used by the instruction.

11. A computer system for facilitating processing within a computing environment, the computer system comprising:
a memory; and
a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
obtaining an instruction to perform a sort operation, the instruction being a single architected machine instruction of an instruction set architecture, and the instruction to access one field to be used to designate a location, the location to be used to store one or more output list delineations; and
executing, by a general-purpose processor of the computing environment, the instruction, the executing comprising:
sorting a plurality of input lists to obtain one or more sorted output lists; and
providing as output the one or more sorted output lists and providing the one or more output list delineations, the one or more output list delineations being based on the one or more sorted output lists, wherein an output list delineation of the one or more output list delineations corresponds to a sorted output list of the one or more sorted output lists and includes information relating to the sorted output list, the information including a length of the sorted output list.

12. The computer system of claim 11 , wherein the instruction includes an operation code field including an operation code to specify a sort list operation, and has access to another field to be used to designate another location, the another location to be used in storing the one or more sorted output lists.

13. The computer system of claim 11 , wherein the instruction employs one select register to determine a function to be performed by the instruction.

14. The computer system of claim 13 , wherein the function is selected from a group of functions consisting of: a query available functions function, a sort fixed-length records function, and a sort variable-length records function.

15. The computer system of claim 11 , wherein the instruction includes an operation code field including an operation code to specify a sort list operation; one register field including a designation of one register, the one register including an address used in storing the one or more output list delineations; and another register field including a designation of another register, the another register including an address used in storing the one or more sorted output lists, and wherein the instruction employs a first implied register to determine a function to be performed by the instruction and a second implied register to locate a parameter block in memory used by the instruction.

16. A computer-implemented method facilitating processing within a computing environment, the computer-implemented method comprising:
obtaining an instruction to perform a sort operation, the instruction being a single architected machine instruction of an instruction set architecture, and the instruction to access one field to be used to designate a location, the location to be used to store one or more output list delineations; and
executing, by a general-purpose processor of the computing environment, the instruction, the executing comprising:
sorting a plurality of input lists to obtain one or more sorted output lists; and
providing as output the one or more sorted output lists and providing the one or more output list delineations, the one or more output list delineations being based on the one or more sorted output lists, wherein an output list delineation of the one or more output list delineations corresponds to

Assignees

• IBM

Inventors

• Giamei Bruce C
• Recktenwald Martin
• Schmidt Donald W
• Siegel Timothy
• Puranik Aditya N
• Farrell Mark S
• Jacobi Christian
• Bradbury Jonathan D
• Zoellin Christian

Classifications

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title

• G06F9/30032 Primary

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F16/2443 Primary

  Stored procedures · CPC title