Instruction merging optimization

Patent metadata

Field	Value
Publication number	US-9513916-B2
Application number	US-201313790632-A
Country	US
Kind code	B2
Filing date	Mar 8, 2013
Priority date	Mar 28, 2012
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A computer-implemented method includes determining that two or more instructions of an instruction stream are eligible for optimization, where the two or more instructions include a memory load instruction and a data processing instruction to process data based on the memory load instruction. The method includes merging, by a processor, the two or more instructions into a single optimized internal instruction and executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction.

First claim

What is claimed is:

1. A computer-implemented method comprising:
determining that two or more instructions of an instruction stream are eligible for optimization, the two or more instruction including a memory load instruction and a data processing instruction to process data based on the memory load instruction;
merging, by a processor, the two or more instructions into a single optimized internal instruction, wherein the single optimized internal instruction comprises a single stored rename register identifier;
storing the single optimized internal instruction in a single slot in an issue queue; and
executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction, the executing including executing the memory load instruction followed by the data processing instruction.

2. The computer-implemented method of claim 1 , wherein executing the single optimized internal instruction includes executing the single optimized internal instruction instead of two or more separate internal instructions corresponding to the two or more instructions of the instruction stream.

3. The computer-implemented method of claim 1 , wherein executing the single optimized internal instruction further includes fetching the single optimized internal instruction from the queue and generating from the single optimized internal instruction two or more separate internal instructions corresponding to the memory load instruction and the data processing instruction.

4. The computer-implemented method of claim 1 , wherein determining that the two or more instructions are eligible for optimization includes determining that a target destination of the memory load instruction is the same as an operand location of the data processing instruction.

5. The computer-implemented method of claim 1 , wherein executing the single optimized internal instruction further includes executing the single optimized internal instruction twice, executing the memory load instruction the first time the single optimized internal instruction is executed, and executing the data processing instruction the second time the single optimized internal instruction is executed.

6. A computer-implemented method comprising:
determining that two or more instructions of an instruction stream are eligible for optimization, the two or more instruction including a memory load instruction and a data processing instruction to process data based on the memory load instruction;
merging, by a processor, the two or more instructions into a single optimized internal instruction, wherein the single optimized internal instruction comprises a single stored rename register identifier;
storing the single optimized internal instruction in a single slot in an issue queue; and

executing the single optimized internal instruction to perform a memory load function and a data processing function corresponding to the memory load instruction and the data processing instruction, the executing including executing the memory load instruction followed by the data processing instruction,
wherein merging the two or more instructions into the single optimized internal instruction includes forming the single optimized internal instruction to have a first instruction portion corresponding to a first one of the two or more instructions and a second instruction portion corresponding to a second one of the two or more instructions, and
wherein merging the two or more internal instructions into the single optimized internal instruction includes omitting from the second instruction portion data corresponding to at least one of an operand location and a destination of the second one of the two or more instructions that is the same as a target destination of the first one of the two or more internal instructions.

Assignees

• IBM

Inventors

• Gschwind Michael K
• Salapura Valentina

Classifications

• G06F9/384 Primary

  Register renaming · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title

• G06F9/3017 Primary

  Runtime instruction translation, e.g. macros · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3804 Primary

  for branches, e.g. hedging, branch folding · CPC title