Sharing register file usage between fused processing resources

Patent metadata

Field	Value
Publication number	US-11221848-B2
Application number	US-201916582406-A
Country	US
Kind code	B2
Filing date	Sep 25, 2019
Priority date	Sep 25, 2019
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of processing resources including a first processing resource and a second processing resource;
a shared local memory communicatively coupled to the first processing resource by a first data bus and the second processing resource by a second data bus; and
a first memory arbiter communicatively coupled to the shared local memory and to the first processing resource and the second processing resource; and
a processor to:
receive an instruction to initiate a matrix multiplication operation;
cause the first memory arbiter to write a first set of matrix data from the shared local memory into a first set of registers; and
share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation.

2. The apparatus of claim 1 , wherein the first processing resource and the second processing resource are fused.

3. The apparatus of claim 2 , the processor to:
allocate a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

4. The apparatus of claim 3 , the processor to:
write a second set of matrix data into a second set of registers.

5. The apparatus of claim 4 , the processor to:
generate a signal to execute the matrix multiplication operation using the first processing resource and the second processing resource.

6. The apparatus of claim 5 , wherein:
the first processing resource generates a first output which represents a matrix multiplication of the first portion of the first set of matrix data and the second set of matrix data; and
the second processing resource generates a second output which represents a matrix multiplication of the second portion of the first set of matrix data and the second set of matrix data.

7. The apparatus of claim 6 , the processor to:
store the first output and the second output in a third set of registers.

8. A non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to:
receive an instruction to initiate a matrix multiplication operation on a plurality of processing resources including a first processing resource and a second processing resource;
cause a first memory arbiter communicatively coupled to the shared local memory and to the first processing resource and the second processing resource to write a first set of matrix data into a first set of registers of a shared local memory communicatively coupled to the first processing resource and the second processing resource; and
share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation.

9. The non-transitory machine readable medium of claim 8 , wherein the first processing resource and the second processing resource are fused.

10. The non-transitory machine readable medium of claim 9 , further comprising instructions which configure the processor to:
allocate a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

11. The non-transitory machine readable medium of claim 8 , further comprising instructions which configure the processor to:
write a second set of matrix data into a second set of registers.

12. The non-transitory machine readable medium of claim 11 , further comprising instructions which configure the processor to:
generate a signal to execute the matrix multiplication operation using the first processing resource and the second processing resource.

13. The non-transitory machine readable medium of claim 12 , wherein:
the first processing resource generates a first output which represents a matrix multiplication of the first portion of the first set of matrix data and the second set of matrix data; and
the second processing resource generates a second output which represents a matrix multiplication of the second portion of the first set of matrix data and the second set of matrix data.

14. The non-transitory machine readable medium of claim 13 , further comprising instructions which configure the processor to:
store the first output and the second output in a third set of registers.

15. A computer-implemented method, comprising:
receiving an instruction to initiate a matrix multiplication operation on a plurality of processing resources including a first processing resource and a second processing resource;
causing a first memory arbiter communicatively coupled to the shared local memory and to the first processing resource and the second processing resource to write a first set of matrix data into a first set of registers of a shared local memory communicatively coupled to the first processing resource and the second processing resource; and
sharing the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation.

16. The method of claim 15 , wherein the first processing resource and the second processing resource are fused.

17. The method of claim 16 , further comprising:
allocating a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

18. The method of claim 15 , further comprising:
writing a second set of matrix data into a second set of registers.

19. The method of claim 18 , further comprising:
generating a signal to execute the matrix multiplication operation using the first processing resource and the second processing resource.

20. The method of claim 19 , wherein:
the first processing resource generates a first output which represents a matrix multiplication of the first portion of the first set of matrix data and the second set of matrix data; and
the second processing resource generates a second output which represents a matrix multiplication of the second portion of the first set of matrix data and the second set of matrix date.

21. The method of claim 20 , further comprising:
storing the first output and the second output in a third set of registers.

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam
• George Varghese
• Ray Joydeep
• Garg Ashutosh
• Parra Jorge
• Shah Shubh
• Marwaha Shubra

Classifications

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title

• G06N3/045

  Combinations of networks · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title