Mid power mode for an oscillator

Patent metadata

Field	Value
Publication number	US-11221643-B2
Application number	US-201716080464-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.

First claim

What is claimed is:

1. A method to generate different clock signals of-different qualities in a device, the method comprising:
determining a power mode in which the device is operating; and
based on the power mode of the device,
controlling oscillator circuitry to cause the oscillator circuitry to consume either a lower amount of power or a higher amount of power, the oscillator circuitry being configured to generate an oscillator signal, and
controlling, independently of the controlling of the oscillator circuitry, a shaper circuitry having a first amplifier stage and a second amplifier stage that shape the oscillator signal, to consume either the lower amount of power or the higher amount of power,

wherein the lower amount of power and the higher amount of power are different from one another, and
when controlling the shaper circuitry to transition from consuming the lower amount of power to consuming the higher amount of power, providing the higher amount of power to second amplifier stage and then to both the first amplifier stage and the second amplifier stage.

2. The method of claim 1 , comprising switching between power modes of the device within a WiFi frame time.

3. The method of claim 1 , comprising determining the power mode of the device based on a mode of operation of one or more circuitries in the device.

4. The method of claim 1 , comprising in response to determining that a Bluetooth connectivity application circuitry in the device is operating in a low power mode and a wireless fidelity (WiFi) connectivity application circuitry in the device is operating in a beacon mode, controlling the oscillator circuitry to consume the lower amount of power and controlling the shaper circuitry to consume the lower amount of power.

5. The method of claim 1 , comprising in response to determining that a Bluetooth connectivity application circuitry in the device is operating in a performance mode and a wireless fidelity (WiFi) application in execution on the device is operating in a full performance mode, controlling the oscillator circuitry to consume the higher amount of power and controlling the shaper circuitry to consume the higher amount of power.

6. The method of claim 1 , comprising in response to determining that a Bluetooth connectivity application circuitry in the device is operating in a performance mode and a wireless fidelity (WiFi) connectivity application circuitry in the device is operating according to a high modulation scheme, controlling the oscillator circuitry to consume the lower amount of power and controlling the shaper circuitry to consume the higher amount of power.

7. The method of claim 1 , comprising determining the power mode of the device based on whether digital circuits, analog circuits, and radio frequency (RF) circuits in the device are active.

8. The method of claim 7 , comprising in response to determining that the radio frequency (RF) circuits are active, controlling the oscillator circuitry to consume the higher amount of power and controlling the shaper circuitry to consume the higher amount of power.

9. The method of claim 7 , comprising in response to determining that the analog circuits are active and the radio frequency (RF) circuits are not active, controlling the oscillator circuitry to consume the lower amount of power and controlling the shaper circuitry to consume the lower amount of power.

10. The method of claim 7 , comprising determining that a respective one of the digital circuits, the analog circuits, or the radio frequency (RF) circuits is active when a clocking request is received from the respective one of the digital circuits, the analog circuits, and the radio frequency (RF) circuits.

11. The method of claim 7 , comprising determining that a respective one of the digital circuits, the analog circuits, or the radio frequency (RF) circuits is not active when a clocking request is not received from the respective one of the digital circuits, the analog circuits, and the radio frequency (RF) circuits.

12. A clock signal generation system for a device, comprising:
control circuitry;
generator circuitry configured to generate a signal having a predetermined frequency;
two-level shaper circuitry configured to shape the signal to generate a first clock signal or a second clock signal, wherein the first clock signal is characterized by a lower quality than the second clock signal, the two-level shaper circuitry having a first amplifier stage and a second amplifier stage that shape the signal;
multi-mode regulator circuitry having
a mid-power mode low dropout (LDO) regulator that consumes a first amount of power and is activated by the control circuitry to provide a lower power level; and
a high-power mode LDO regulator that consumes a second amount of power and is activated by the control circuitry to provide a higher power level,
the multi-mode regulator circuitry being configured to provide a selected one of the lower power level or the higher power level to the generator circuitry and a selected one of the lower power level or the higher power level to the two-level shaper circuitry; and

the control circuitry being configured to control the generator circuitry, the two-level shaper circuitry, and the multi-mode regulator circuitry, based on a mode selection, to generate and output a selected one of the first clock signal or the second clock signal as an output clock signal,
the control circuitry being further configured to, in response to the device transitioning from a mid power mode to a high power mode, provide the higher power level to the second amplifier stage and then to both the first amplifier stage and the second amplifier stage.

13. The clock signal generation system of claim 12 , wherein the two-level shaper circuitry comprises:
mid power circuitry configured to shape the signal to generate the first clock signal; and
high power circuitry configured to shape the signal to generate the second clock signal.

14. The clock signal generation system of claim 12 , wherein the control circuitry comprises mode control circuitry configured to determine whether the device is operating in a mid power mode in which the first clock signal is output or a high power mode in which the second clock signal is output based on a mode of operation of one or more connectivity application circuitries in the device.

15. The clock signal generation system of claim 12 , wherein the control circuitry comprises mode control circuitry configured to determine whether the device is operating in a mid power mode in which the first clock signal is output or a high power mode in which the second clock signal is output based on whether digital circuits, analog circuits, and radio frequency (RF) circuits in the device are active.

16. The clock signal generation system of claim 12 , further comprising:
clock distribution circuitry configured to select one of the first clock signal or the second clock signal as an output clock signal; and
wherein the multi-mode regulator circuitry is configured to provide the selected one of a lower power level power or a higher power level to the clock distribution circuitry.

17. Oscillator circuitry, comprising:
control circuitry configured to determine a mode of operation of a device that uses clock signals generated by the oscillator circuitry;
multi-mode regulator circuitry configured to output one of a first power level or a second power level based on the mode of operation, the first power level being lower than the second power level;
generator circuitry configured to receive power from th

Assignees

• Apple Inc

Inventors

• Malevsky Sharon
• Gidoni Tomer
• Porat Shahar
• Eshkoli Ayal
• Romano Tom
• Brendel Johannes
• Meyer Stefan

Classifications

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• H04W52/02

  Power saving arrangements · CPC title

• H03B2200/0082

  Lowering the supply voltage and saving power · CPC title