Magnetoresistive memory device and method for manufacturing magnetoresistive memory device

Patent metadata

Field	Value
Publication number	US-11217745-B2
Application number	US-201916352393-A
Country	US
Kind code	B2
Filing date	Mar 13, 2019
Priority date	Sep 6, 2018
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

According to one embodiment, a method for manufacturing a magnetoresistive memory device includes forming a first layer stack on a substrate. A second layer stack including a first ferromagnet is formed on the first layer stack. A mask including a first portion and an opening is formed above the second layer stack. The second layer stack is etched with an ion beam that travels through the opening. The first layer stack is etched by reactive ion etching through the opening.

First claim

What is claimed is:

1. A method for manufacturing a magnetoresistive memory device, the method comprising:
forming a first conductor over a substrate;
forming a first layer stack on the first conductor, the first layer stack including a switching element;
forming a second layer stack on the first layer stack, the second layer stack including a first ferromagnet;
forming a mask above the second layer stack, the mask including a first portion and an opening;
etching the second layer stack with an ion beam that travels through the opening to form a third layer stack;
forming an insulator which continuously covers a side surface of the third layer stack and a portion of a side surface of the first layer stack; and
etching the first layer stack by reactive ion etching through the opening to form a fourth layer stack, the fourth layer stack having a smaller diameter in an upper section thereof than a diameter in a lower section thereof such that the insulator and the lower section of the fourth layer stack form a continuous surface,
wherein the first layer stack includes a second conductor in a top portion of the first layer stack, and the forming of the insulator includes forming the insulator which continuously covers the side surface of the third layer stack and a portion of a side surface of the second conductor,
wherein the forming of the insulator includes forming the insulator which continuously covers the side surface of the third layer stack and the portion of the side surface of the second conductor except a side surface of the switching element.

2. The method according to claim 1 , wherein:
the etching of the second layer stack includes forming, in the second layer stack, a hole through the second layer stack from an upper surface to a lower surface of the second layer stack to form the third layer stack from the second layer stack.

3. The method according to claim 1 , wherein:
the etching of the first layer stack includes forming, in the first layer stack, a hole through the first layer stack from an upper surface to a lower surface of the first layer stack.

4. The method according to claim 1 , wherein:
the ion beam has a first angle relative to an axis perpendicular to a surface of the substrate.

5. The method according to claim 4 , wherein:
the first angle has a magnitude with which the ion beam is blocked by the mask and does not reach a lower surface of the first layer stack inside the opening.

6. The method according to claim 1 , wherein:
L/D >1 is satisfied where D represents a distance between a lower surface of the fourth layer stack and a lower surface of a fifth layer stack adjacent to the fourth layer stack, and L represents a length from an upper surface of the second layer stack to the lower surface of the first layer stack.

7. The method according to claim 6 , wherein:
the second layer stack includes the first ferromagnet, a second ferromagnet, a nonmagnet between the first ferromagnet and the second ferromagnet.

8. The method according to claim 1 , wherein:
when a voltage lower than a first value is applied to the switching element, the switching element exhibits a first resistance, and when a voltage equal to or higher than the first value is applied to the switching element, the switching element exhibits a second resistance.

9. The method according to claim 1 , wherein the forming of the first layer stack includes:
forming a second conductor on the first conductor,
forming the switching element on the second conductor, and
forming a third conductor on the switching element.

10. The method according to claim 9 , wherein:
the forming of the first conductor includes forming two first conductors separated from each other,
the second conductor is formed to extend on upper surfaces of the first conductors,
the etching of the first layer stack includes partially removing the first layer stack in an area over an area between the first conductors.

11. The method according to claim 1 , wherein:
the etching of the second layer stack includes etching a part of a top surface of the first layer stack to expose the portion of the side surface of the first layer stack in the opening.

12. The method according to claim 11 , wherein:
the forming of the insulator includes forming the insulator further on the part of the top surface of the first layer stack in the opening, and
the etching of the first layer stack includes etching a part of the insulator on the part of the top surface of the first layer stack.

13. The method according to claim 12 , wherein:
the etching of the first layer stack uses a part of the insulator on the side surface of the third layer stack as a mask.

14. The method according to claim 1 , wherein:
the second conductor is on the switching element.

15. The method according to claim 1 , wherein:
the etching of the second layer stack with the ion beam is performed by a first etching method that enables formation of a structure with a first aspect ratio,
the etching of the first layer stack by the reactive ion etching is performed by a second etching method that enables formation of a structure with a second aspect ratio, and
the second aspect ratio is higher than the first aspect ratio.

16. The method according to claim 1 , wherein:
the third layer stack has an aspect ratio lower than an aspect ratio of the fourth layer stack.

Assignees

• Toshiba Memory Corp

Inventors

• Ito Yuichi
• Matsuo Kouji

Classifications

• H10N50/85

  Materials of the active region · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/228

  Electricity · mapped topic

• H01L43/10

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic