Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11217669-B2
Application number	US-202016837408-A
Country	US
Kind code	B2
Filing date	Apr 1, 2020
Priority date	Jul 23, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a recess;
an interface insulation pattern conformal to a surface of the recess;
a gate insulation pattern on the interface insulation pattern, the gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide; and
a threshold voltage controlling metal pattern on the gate insulation pattern;
a conductive pattern on the threshold voltage controlling metal pattern, the conductive pattern including a polysilicon pattern doped with N-type or P-type impurities and an upper metal pattern including a metal having a resistance lower than that of the polysilicon pattern; and
impurity regions serving as source/drain regions in the substrate on adjacent sides of the recess,
wherein first dopants are within and at at least one surface of the gate insulation pattern and at an upper surface of the interface insulation pattern contacting the gate insulation pattern, and the first dopants include at least fluorine, and
wherein a stacked structure including the interface insulation pattern, the gate insulation pattern, the threshold voltage controlling metal pattern and the conductive pattern is in the recess.

2. The semiconductor device of claim 1 , wherein the polysilicon pattern doped with N-type or P-type impurities directly contacts threshold voltage controlling metal pattern.

3. The semiconductor device of claim 1 , wherein the conductive pattern further includes a lower polysilicon pattern, and
wherein the lower polysilicon pattern directly contacts the threshold voltage controlling metal pattern, the lower polysilicon pattern is disposed between the threshold voltage controlling metal pattern and a polysilicon pattern doped with N-type or P-type impurities, and the lower polysilicon pattern includes second dopants including at least fluorine.

4. The semiconductor device of claim 1 , wherein the first dopants further include nitrogen, phosphorus, boron, or gallium.

5. The semiconductor device of claim 1 , further comprising third dopants included in threshold voltage controlling metal pattern, and wherein the third dopants are the same dopants as the first dopants.

6. The semiconductor device of claim 1 , wherein an upper surface of the conductive pattern is higher than an upper surface of the substrate.

7. A semiconductor device, comprising:
a substrate including a recess;
a gate insulation pattern conformal to the substrate; and
a conductive pattern on the gate insulation pattern, and the conductive pattern including a polysilicon pattern doped with N-type or P-type impurities and an upper metal pattern,
wherein first dopants are within the gate insulation pattern and at an upper and a lower interface of the gate insulation pattern, and the first dopants include at least fluorine, and
wherein a stacked structure including the gate insulation pattern and the conductive pattern is in the recess.

8. The semiconductor device of claim 7 , wherein the gate insulation pattern includes silicon oxide or an oxide having a dielectric constant higher than that of silicon oxide.

9. The semiconductor device of claim 7 , wherein an upper surface of the conductive pattern is higher than an upper surface of the substrate.

10. The semiconductor device of claim 7 , wherein the first dopants further include nitrogen, phosphorus, boron or gallium.

Assignees

• Samsung Electronics Co Ltd

Inventors

• An Hokyun
• Kim Bumsoo
• Kim Hyunseung
• Jiao Guangfan

Classifications

• H10P32/20

  Diffusion for doping of insulating layers · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title