Semiconductor device and method for forming a semiconductor device

Patent metadata

Field	Value
Publication number	US-11217500-B2
Application number	US-201916379289-A
Country	US
Kind code	B2
Filing date	Apr 9, 2019
Priority date	Apr 10, 2018
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a contact metallization layer arranged on a semiconductor substrate;
an inorganic passivation structure arranged on the semiconductor substrate; and
an organic passivation layer,
wherein a first part of the organic passivation layer is located laterally between the contact metallization layer and the inorganic passivation structure,
wherein a second part of the organic passivation layer is located on top of the inorganic passivation structure,
wherein the first part of the organic passivation layer is located vertically closer to the semiconductor substrate than the second part of the organic passivation layer,
wherein a third part of the organic passivation layer is located directly over the contact metallization layer, and
wherein the inorganic passivation structure is one continuous layer that contacts the semiconductor substrate
wherein the contact metallization layer comprises a first edge side that extends from an upper surface of the contact metallization layer towards the semiconductor substrate,
wherein the inorganic passivation structure comprises a second edge side that extends from an upper surface of the inorganic passivation structure towards semiconductor substrate,
wherein the first and second edge sides define a lateral gap between the inorganic passivation structure and the contact metallization layer,
wherein the first part of the organic passivation layer extends into the lateral gap, and
wherein the second edge side is a closest surface of the inorganic passivation material to the contact metallization layer.

2. The semiconductor device of claim 1 , wherein a thickness of the inorganic passivation structure is at least 500 nm.

3. The semiconductor device of claim 1 , wherein the inorganic passivation structure comprises at least a silicon oxide layer having a thickness of at least 300 nm and at most 5 μm.

4. The semiconductor device of claim 1 , wherein the inorganic passivation structure comprises at least a nitride layer having a thickness of at least 300 nm and at most 900 nm.

5. The semiconductor device of claim 1 , wherein a lateral distance between the inorganic passivation structure and the contact metallization layer is larger than a thickness of the contact metallization layer.

6. The semiconductor device of claim 1 , wherein a lateral distance between the inorganic passivation structure and the contact metallization layer is less than a width of the inorganic passivation structure.

7. The semiconductor device of claim 1 , wherein a lateral distance between the inorganic passivation structure and an edge of the semiconductor substrate is at least 10 μm.

8. The semiconductor device of claim 1 , wherein a thickness and/or a material of the inorganic passivation structure is configured such that an electric field at a surface of the inorganic passivation structure is at least 500 kV/cm in a blocking state of an electrical structure formed at the semiconductor substrate.

9. The semiconductor device of claim 1 , wherein the organic passivation layer is a polyimide layer having a thickness of at least 1 μm and at most 50 μm.

10. The semiconductor device of claim 1 , wherein a thickness and/or a material of the organic passivation structure is configured such that an electric field at a surface of the organic passivation layer is at most 500 kV/cm in a blocking state of an electrical structure formed at the semiconductor substrate.

11. The semiconductor device of claim 1 , further comprising:
an adhesion layer,
wherein a first part of the adhesion layer is arranged between the contact metallization layer and the organic passivation layer,
wherein a second part of the adhesion layer is arranged between the inorganic passivation structure and the organic passivation layer,
wherein the adhesion layer extends at least from the first part of the adhesion layer to the second part of the adhesion layer.

12. The semiconductor device of claim 11 , wherein the adhesion layer has a thickness of at most 100 nm and at least 10 nm.

13. The semiconductor device of claim 1 , further comprising:
a mold compound structure in contact with the organic passivation layer.

14. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises:
a drift region of an electrical structure comprising dopants of a first conductivity type; and
an edge termination region comprising dopants of a second conductivity type,
wherein the edge termination region extends laterally from a contact region towards an edge of the semiconductor substrate at least partially beneath the inorganic passivation structure,
wherein the edge termination region is ohmically connected to the contact metallization layer.

15. The semiconductor device of claim 14 , wherein a lateral distance between the inorganic passivation structure and the edge of the semiconductor substrate is smaller than a lateral distance between the edge termination region and the edge of the semiconductor substrate.

16. The semiconductor device of claim 1 , further comprising:
a bond wire or solder structure in contact with the contact metallization layer.

17. The semiconductor device of claim 1 , wherein the semiconductor substrate is a wide band-gap material semiconductor substrate.

18. The semiconductor device of claim 1 , further comprising:
an electrical structure formed at the semiconductor substrate and having a breakdown voltage at least 100V.

19. The semiconductor device of claim 1 , wherein the organic passivation layer continuously covers the inorganic passivation layer and at least parts of the contact metallization layer.

20. The semiconductor device of claim 1 , further comprising:
an intermediate oxide layer,
wherein a first part of the intermediate oxide layer is arranged vertically between the contact metallization layer and the semiconductor substrate,
wherein a second part of the intermediate oxide layer is arranged vertically between the inorganic passivation structure and the semiconductor substrate,
wherein the intermediate oxide layer extends at least from the first part of the intermediate oxide layer to the second part of the intermediate oxide layer.

21. The semiconductor device of claim 20 , wherein the inorganic passivation structure comprises a nitride layer, and wherein the first part of the organic passivation layer is located vertically closer to the intermediate oxide layer than the second part of the organic passivation layer.

22. The semiconductor device of claim 20 , wherein the inorganic passivation structure comprises a silicon oxide layer and a silicon nitride layer, and wherein the silicon oxide layer is arranged vertically between the silicon nitride layer and the intermediate oxide layer.

23. A semiconductor device, comprising:
a barrier layer comprising a titanium sublayer and a titanium aluminum alloy sublayer; and
a contact metallization layer comprising aluminum,
wherein at least a part of the titanium sublayer contacts a semiconductor substrate of the semiconductor device and is located between the contact metallization layer and the semiconductor substrate of the semiconductor device,
wherein at least a part of the titanium aluminum alloy sublayer is in contact with the titanium sublayer and the contact metallization layer,
wherein a portion of the barrier layer laterally extends past an edge side of the contact metallization layer, and
wherein th

Assignees

• Infineon Technologies Ag

Inventors

• Konrath Jens Peter
• Bergner Wolfgang
• Esteve Romain
• Gaisberger Richard
• Grasse Florian
• Hilsenbeck Jochen
• Joshi Ravi Keshav
• Kramp Stefan
• Krivec Stefan
• Lupina Grzegorz
• Narahashi Hiroshi
• Voerckel Andreas
• Woehlert Stefan

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/47

  comprising organic materials, e.g. plastics or resins · CPC title

• H10W74/43

  comprising oxides, nitrides or carbides, e.g. ceramics or glasses · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title