Error correction code processing and data shaping for reducing wear to a memory

Patent metadata

Field	Value
Publication number	US-10114549-B2
Application number	US-201615073373-A
Country	US
Kind code	B2
Filing date	Mar 17, 2016
Priority date	Mar 17, 2016
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.

First claim

What is claimed is:

1. A data storage device comprising:
a memory; and
a controller comprising a memory interface and a data shaping engine, the controller configured to:
apply a mapping via the data shaping engine to input data to generate transformed data, the input data including one or more m-tuples of bits with a first number of bit values that represent a particular logical state in the memory, the particular logical state being a high-wear voltage of the memory, the transformed data including one or more n-tuples of bits with a second number of bit values that represent the particular logical state,
wherein n is greater than m,
wherein a relationship of a gray coding of m-tuples of bits to a gray coding of n-tuples of bits is indicated by the mapping,
wherein the transformed data reduces wear at the memory based on the second number of bit values being less than the first number of bit values, and
write, with the memory interface, the transformed data to the memory to store the one or more n-tuples of bits with the second number of bit values by modifying states of storage elements of the memory so that the transformed data is readable via detection by read circuitry of the modified states.

2. The data storage device of claim 1 , wherein the gray coding of m-tuples of bits includes 2 m m-tuples of bits, and wherein the gray coding of n-tuples of bits includes a subset of 2 n possible n-tuples of bits.

3. The data storage device of claim 1 , wherein the controller further comprises an error correction code (ECC) engine, wherein the ECC engine is configured to generate one or more ECC codewords based on user data, and wherein the input data comprises the one or more ECC codewords.

4. The data storage device of claim 3 , wherein the controller further comprises a data compression engine configured to congress the user data prior to providing the user data to the ECC engine, wherein the data compression engine is further configured to compress the user data in accordance with a data throughput setting, wherein the ECC engine is further configured to generate the one or more ECC codewords in accordance with a bit error rate setting, and wherein the data shaping engine is configured to generate the transformed data having the same size as the user data prior to compression.

5. The data storage device of claim 1 , wherein, in the gray coding of m-tuples of bits and the gray coding of n-tuples of bits, successive tuples of bits differ by a single bit.

6. The data storage device of claim 1 , wherein the controller is further configured to store a key associated with the mapping at the memory, and wherein the key is an error correction code processed at the controller prior to storage.

7. The data storage device of claim 1 , wherein the mapping includes a one-to-one encoding mapping of m-tuples of bits to n-tuples of bits and a many-to-one decoding mapping of groups of n-tuples of bits to m-tuples of bits.

8. The data storage device of claim 7 , wherein the controller is further configured to read a first n-tuple of bits of the transformed data from the memory, and wherein the data shaping engine is configured to decode the first n-tuple of bits into a m-tuple of bits that corresponds to the first n-tuple of bits with the many-to-one decoding mapping.

9. The data storage device of claim 1 , wherein, to apply, with the data shaping engine, the mapping to the input data to generate the transformed data, the data shaping engine is configured to select the mapping from a plurality of mappings stored in a controller memory of the controller.

10. The data storage device of claim 1 , wherein the first number of bit values and the second number of bit values comprise single-bit values, and wherein the particular logical state is indicated by a single bit.

11. The data storage device of claim 1 , wherein the first number of bit values and the second number of bit values comprise multi-bit values, and wherein the particular logical state is indicated by multiple bits.

12. A data storage device comprising:
a memory; and
a controller comprising a memory interface and a data shaping and error correction code (ECC) engine, the controller configured to
use the data shaping and ECC engine to apply a mapping to input data to generate transformed data, the input data including one or more m-tuples of bits with a first number of bit values that represent a particular logical state in the memory, the particular logical state being a high-wear voltage of the memory, the transformed data including one or more n-tuples of bits with a second number of bit values that represent the particular logical state,
wherein n is greater than m,
wherein the mapping includes a one-to-one encoding mapping and a many-to-one decoding mapping,
wherein the transformed data reduces wear at the memory based on the second number of bit values being less than the first number of bit values, and
write, with the memory interface, the transformed data to the memory to store the one or more n-tuples of bits with the second number of bit values by modifying states of storage elements of the memory so that the transformed data is readable via detection by read circuitry of the modified states.

13. The data storage device of claim 12 , wherein the data shaping and ECC engine is configured to maintain a particular difference level between at least two n-tuples of bits of the transformed data that correspond to different m-tuples of bits of the input data according to the many-to-one decoding mapping, and wherein the particular difference level is based on a number of bits that are different between the at least two n-tuples of bits or a position of the bits that are different between the at least two n-tuples of bits.

14. The data storage device of claim 12 , wherein the controller further comprises a data compression engine configured to compress the input data prior to providing the input data to the data shaping and ECC engine.

15. The data storage device of claim 12 , wherein the controller is further configured to store a key associated with the mapping at the memory, and wherein the key is an error correction code processed at the controller prior to storage.

16. The data storage device of claim 15 , wherein the controller is further configured to read a representation of the transformed data from the memory, wherein the data shaping engine is configured to decode a first n-tuple of bits of the representation of the transformed data to generate first de-shaped data, and wherein the first de-shaped data includes a first m-tuple of bits having a particular value.

17. The data storage device of claim 16 , wherein the data shaping engine is configured to decode a second n-tuple of bits of the representation of the transformed data to generate second de-shaped data, and wherein the second de-shaped data includes a second m-tuple of bits having the particular value.

18. The data storage device of claim 16 , wherein the first de-shaped data is generated without determining a difference between the first n-tuple of bits and one or more n-tuples of bits in the many-to-one decoding mapping.

19. The data storage device of claim 12 , wherein each possible n-tuple of bits is mapped to an m-tuple of bits in the many-to-one decoding mapping.

20. The data storage device of claim 12 , wherein the first number of bit values and the second number of bit values comprise single-bit values, and wherein the particular logical state is indicated by a single bit.

2

Assignees

• Sandisk Technologies Llc

Inventors

• Alrod Idan
• Sharon Eran
• Navon Ariel

Classifications

• G11C16/34

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F2212/403

  Error protection encoding, e.g. using parity or ECC codes · CPC title