Array substrate, method for manufacturing the same, and display apparatus

Patent metadata

Field	Value
Publication number	US-11215893-B2
Application number	US-201816304737-A
Country	US
Kind code	B2
Filing date	Feb 28, 2018
Priority date	Jul 4, 2017
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

Embodiments of the present disclosure provide an array substrate, a method for manufacturing the same, and a display apparatus. The array substrate includes a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region. Each data lead corresponds to one pad structure. The pad structure includes at least two pad electrodes insulated from each other. In the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths.

First claim

What is claimed is:

1. An array substrate comprising a plurality of pad structures located in a bonding region and a plurality of data leads located in a lead region, each data lead corresponding to one pad structure,
wherein the pad structure comprises at least two pad electrodes insulated from each other, and in the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths,
wherein the array substrate further comprises a base substrate, and the at least two pad electrodes comprise a first pad electrode and a second pad electrode sequentially disposed on the base substrate in a direction perpendicular to the base substrate and insulated from each other, and
wherein the array substrate further comprises:
a first insulating layer located between the first pad electrode and the second pad electrode;
a second insulating layer covering the first insulating layer and the second pad electrode;
a first via located in the first insulating layer and the second insulating layer and reaching the first pad electrode and a second via located in the second insulating layer and reaching the second pad electrode; and
a first conductive electrode and a second conductive electrode located on the second insulating layer, wherein the first conductive electrode is electrically connected to the first pad electrode through the first via, and wherein the second conductive electrode is electrically connected to the second pad electrode through the second via.

2. The array substrate according to claim 1 , wherein an extending direction of the first pad electrode is the same as an extending direction of the second pad electrode, wherein an orthographic projection of the second pad electrode on the base substrate overlaps with a portion, adjacent to the lead region, of an orthographic projection of the first pad electrode on the base substrate, and wherein one end of the first pad electrode and one end of the second pad electrode adjacent to the lead region are both electrically connected to the data lead.

3. The array substrate according to claim 1 , wherein an orthographic projection of the first pad electrode on the base substrate does not overlap with an orthographic projection of the second pad electrode on the base substrate,
wherein the first pad electrode comprises a first sub-portion and a second sub-portion, wherein the first sub-portion is located at one end of the second pad electrode facing away from the data lead, wherein an extending direction of the first sub-portion is the same as the extending direction of the second pad electrode, wherein the second sub-portion is located on a side of the second pad electrode in a direction perpendicular to the extending direction, wherein one end of the second sub-portion is connected to the first sub-portion, and wherein the other end of the second sub-portion is electrically connected to the data leads, and
wherein one end of the second pad electrode adjacent to the lead region is electrically connected to the data lead.

4. The array substrate according to claim 1 , wherein the data lead is formed in the same layer as the first pad electrode, and wherein the array substrate further comprises a third via located in the first insulating layer and the second insulating layer and reaching a portion of the data lead adjacent to the bonding region, wherein the second conductive electrode is also electrically connected to the data lead through the third via.

5. The array substrate according to claim 1 , wherein the data lead comprises a first sub-electrode and a second sub-electrode, wherein an orthographic projection of the first sub-electrode on the base substrate overlaps with an orthographic projection of the second sub-electrode on the base substrate, wherein the first sub-electrode is formed in the same layer as the first pad electrode and is connected to the first pad electrode, and wherein the second sub-electrode is formed in the same layer as the second pad electrode and is connected to the second pad electrode,
wherein the array substrate further comprises:
a fourth via located in the first insulating layer and the second insulating layer and reaching a portion of the first sub-electrode away from the bonding region;
a fifth via located in the second insulating layer and reaching a portion of the second sub-electrode away from the bonding region; and
a third conductive electrode located on the second insulating layer, wherein the third conductive electrode electrically connects the first sub-electrode to the second sub-electrode through the fourth via and the fifth via.

6. The array substrate according to claim 5 , wherein the lead region comprises a proximal terminal region at a central position and a distal terminal region at both sides of the proximal terminal region,
wherein the data lead located in the proximal terminal region is a straight line extending in a first direction,
wherein a portion of the data lead located in the distal terminal region adjacent to the bonding region is a straight line extending in the first direction, and a portion of the data lead in the distal terminal region away from the bonding region is an oblique line inclined in a direction facing away from the proximal terminal region, the first direction is the same as an extending direction of a signal line connected to the data lead, and
wherein a length of the second sub-electrode located in the proximal terminal region is smaller than a length of the second sub-electrode located in the distal terminal region.

7. The array substrate according to claim 1 , further comprising a gate line and a data line, wherein the gate line is formed in the same layer as the first pad electrode, and wherein the data line is formed in the same layer as the second pad electrode.

8. The array substrate according to claim 4 , further comprising a conductive protective layer covering the second conductive electrode, wherein an orthographic projection of the conductive protective layer on the base substrate overlaps with an orthographic projection of the third via on the base substrate.

9. A display apparatus comprising the array substrate according to claim 1 .

10. A method for manufacturing the array substrate according to claim 1 , the method comprising:
providing a base substrate comprising the bonding region and the lead region;
forming the plurality of pad structures in the bonding region on the base substrate, wherein the pad structure comprises at least two pad electrodes insulated from each other; and
forming the plurality of data leads in the lead region on the base substrate, wherein each data lead corresponds to one pad structure, and in the pad structure, each pad electrode is electrically connected to the data lead corresponding to the pad structure, respectively, to form different signal writing paths,
wherein the method for forming the pad structure comprises:
forming a first metal layer on the base substrate;
patterning the first metal layer to form a first pad electrode;
forming a first insulating layer to cover the base substrate and the first pad electrode;
forming a second metal layer on the first insulating layer;
patterning the second metal layer to form a second pad electrode;
forming a second insulating layer to cover the first insulating layer and the second pad electrode;
patterning the first insulating layer and the second insulating layer to form a first via reaching the first pad electrode and a second via reaching the second pad electrode;
forming a conductive layer on the second insulating layer to fill the first via and the second via; and
patterning the conduc

Assignees

• Boe Technology Group Co Ltd
• Chongqing Boe Optoelectronics Tech Co Ltd

Inventors

• Li Yunze
• Yang Ni
• Qi Zhijian
• Wang Xiaoyuan
• Li Shaoru

Classifications

• G02F1/1345 Primary

  Conductors connecting electrodes to cell terminals · CPC title

• G02F1/13458 Primary

  Terminal pads · CPC title

• G02F1/136295 Primary

  Materials; Compositions; Manufacture processes · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title