Array substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-11215890-B2
Application number	US-201916763565-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Nov 19, 2018
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

An array substrate is provided. The array substrate includes: a base substrate which is provided with a plurality of sub-pixel regions arranged in multiple rows and columns; a plurality of data lines located on the base substrate, each of the plurality of data lines corresponding to at least one of any column of the sub-pixel regions, any row of the sub-pixel regions including a plurality of sub-pixel region pairs, each of the plurality of sub-pixel region pairs including two adjacent sub-pixel regions, any two of the plurality of sub-pixel region pairs including different sub-pixel regions, and two data lines corresponding to the two sub-pixel regions being located at different sides of the two sub-pixel regions in a row direction; and a common electrode and a plurality of pixel electrodes located on the base substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate, wherein the base substrate is provided with a plurality of sub-pixel regions arranged in multiple rows and columns on the base substrate;
a plurality of data lines, wherein the plurality of data lines are located on the base substrate, each of the plurality of data lines corresponds to at least one of any column of the sub-pixel regions, any row of the sub-pixel regions comprise a plurality of sub-pixel region pairs, each of the plurality of sub-pixel region pairs comprises two adjacent sub-pixel regions, any two of the plurality of sub-pixel region pairs comprise different sub-pixel regions, and two data lines corresponding to the two sub-pixel regions are located at different sides of the two sub-pixel regions in a row direction; and
a common electrode and a plurality of pixel electrodes, which are located on the base substrate; and
wherein the common electrode comprises a plurality of comb-shaped sub-electrodes, the plurality of comb-shaped sub-electrodes is in one-to-one correspondence with the plurality of sub-pixel regions, each of the plurality of comb-shaped sub-electrodes comprises a plurality of parallel strip-shaped structures, the plurality of parallel strip-shaped structures cover a region between two sub-pixel regions, and a transverse electric field is formed between the plurality of pixel electrode and the plurality of parallel strip-shaped structures to reduce an area of an electric-field-free region between the plurality of sub-pixel regions.

2. The array substrate according to claim 1 , wherein the plurality of pixel electrodes are in one-to-one correspondence with the plurality of sub-pixel regions;
an orthographic projection of each of the plurality of pixel electrodes on the base substrate is located in a sub-pixel region corresponding to the pixel electrode;
a minimum distance between two pixel electrodes corresponding to the two sub-pixel regions is greater than or equal to a first specified distance; and
the first specified distance is a minimum distance by which the two pixel electrodes do not affect each other.

3. The array substrate according to claim 1 , wherein the strip-shaped structures in the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions form a first specified angle that is greater than 90° and smaller than 180°.

4. The array substrate according to claim 1 , wherein each of the plurality of comb-shaped sub-electrodes comprises two strip-shaped structure sets, each of the two strip-shaped structure sets comprises a plurality of parallel strip-shaped structures, and strip-shaped structures of the four strip-shaped structure sets in the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions are arranged in an x manner.

5. The array substrate according to claim 1 , wherein an orthographic projection of any one of the plurality of comb-shaped sub-electrodes on the base substrate overlaps a sub-pixel region corresponding to the any one of the plurality of comb-shaped sub-electrodes.

6. The array substrate according to claim 1 , wherein the two comb-shaped sub-electrodes are electrically connected.

7. The array substrate according to claim 1 , in any row of the sub-pixel regions, a distance between the two data lines that are located between any two adjacent sub-pixel regions is greater than or equal to a second specified distance, and the second specified distance is a minimum distance by which the two data lines do not affect each other.

8. The array substrate according to claim 7 , wherein a distance between the two pixel electrodes at two sides of the two data lines is greater than or equal to a fourth specified distance, the fourth specified distance is the sum of the second specified distance, widths of the two data lines and two times of a third specified distance, and the third specified distance is a minimum distance by which the pixel electrodes on the base substrate do not affect the data lines.

9. The array substrate according to claim 1 , wherein the plurality of comb-shaped sub-electrodes is made of a transparent conductive material.

10. The array substrate according to claim 1 , wherein the plurality of pixel electrodes are in one-to-one correspondence with the plurality of sub-pixel regions;
an orthographic projection of each of the plurality of pixel electrodes on the base substrate is located in a sub-pixel region corresponding to the pixel electrode;
a minimum distance between two pixel electrodes corresponding to the two sub-pixel regions is greater than or equal to a first specified distance; and
the first specified distance is a minimum distance by which the two pixel electrodes do not affect each other;
the strip-shaped structures in the two comb-shaped sub-electrodes corresponding to the two sub-pixel regions form a first specified angle that is greater than 90° and smaller than 180°, and the two comb-shaped sub-electrodes are electrically connected; and
an orthographic projection of any one of the plurality of comb-shaped sub-electrodes on the base substrate overlaps a sub-pixel region corresponding to the any one of the plurality of comb-shaped sub-electrodes.

11. A display panel, comprising a color filter substrate, a liquid crystal layer and an array substrate, wherein the array substrate comprises:
a base substrate, wherein the base substrate is provided with a plurality of sub-pixel regions arranged in multiple rows and columns on the base substrate;
a plurality of data lines, wherein the plurality of data lines are located on the base substrate, each of the plurality of data lines corresponds to at least one of any column of the sub-pixel regions; any row of the sub-pixel regions comprise a plurality of sub-pixel region pairs, each of the plurality of sub-pixel region pairs comprises two adjacent sub-pixel regions, any two of the plurality of sub-pixel region pairs comprise different sub-pixel regions, and two data lines corresponding to the two sub-pixel regions are located at different sides of the two sub-pixel regions in a row direction; and
a common electrode and a plurality of pixel electrodes, which are located on the base substrate; and
wherein the common electrode comprises a plurality of comb-shaped sub-electrodes, the plurality of comb-shaped sub-electrodes is in one-to-one correspondence with the plurality of sub-pixel regions, each of the plurality of comb-shaped sub-electrodes comprises a plurality of parallel strip-shaped structures, the plurality of parallel strip-shaped structures cover a region between two sub-pixel regions, and a transverse electric field is formed between the plurality of pixel electrode and the plurality of parallel strip-shaped structures to reduce an area of an electric-field-free region between the plurality of sub-pixel regions.

12. The display panel according to claim 11 , wherein the plurality of pixel electrodes are in one-to-one correspondence with the plurality of sub-pixel regions;
an orthographic projection of each of the plurality of pixel electrodes on the base substrate is located in a sub-pixel region corresponding to the pixel electrode;
the color filter substrate is provided with a first black matrix; and
an orthographic projection of a region between the two pixel electrodes corresponding to the two sub-pixel regions on the base substrate is located in an orthographic projection of the first black matrix on the base substrate.

13. The display panel according to claim 11 , wherein the color filter substrate is provided with a second black matrix and an orthographic projection of a region between the two pixel electrode

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Song Wenhua
• Shi Bo
• Yan Shaning
• Chen Shiqi
• Wang Limiao

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/133512

  Light shielding layers, e.g. black matrix (G02F1/136209 takes precedence) · CPC title

• G02F1/134318

  having a patterned common electrode · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title