Packaged semiconductor devices and packaging methods

Patent metadata

Field	Value
Publication number	US-11211358-B2
Application number	US-201916716078-A
Country	US
Kind code	B2
Filing date	Dec 16, 2019
Priority date	Dec 29, 2015
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.

First claim

What is claimed is:

1. A packaged semiconductor device comprising:
an integrated circuit die;
a first molding material disposed around the integrated circuit die;
a through-via disposed within the first molding material;
a redistribution layer (RDL) coupled to the integrated circuit die and the through via, wherein the integrated circuit die, the through-via, and the first molding material are disposed on a first side of the RDL;
a second molding material disposed over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL; and
an antenna disposed over the second molding material, wherein the antenna is disposed over a sidewall of the first molding material, and wherein the through-via is coupled to a portion of the antenna disposed over the sidewall of the first molding material.

2. The packaged semiconductor device according to claim 1 , wherein the through-via comprises a ground connection for the antenna.

3. The packaged semiconductor device according to claim 1 , wherein the antenna is disposed over a surface of the second molding material, wherein the through-via comprises a first through-via, wherein a second through-via is disposed within the second molding material, wherein the second through-via is coupled to a portion of the antenna disposed over the surface of the second molding material, and wherein the second through-via is coupled to the first through-via by a portion of the RDL.

4. The packaged semiconductor device according to claim 1 , wherein the through-via comprises a first through-via, and wherein a portion of the RDL, a second through-via in the second molding material, or a portion of the RDL and a second through-via in the second molding material comprises a feeding element for the antenna.

5. The packaged semiconductor device according to claim 1 , wherein the antenna comprises an aperture.

6. The packaged semiconductor device according to claim 5 , the aperture extends from a first edge of the antenna to a second edge of the antenna opposite the first edge.

7. The packaged semiconductor device according to claim 1 , wherein the antenna extends continuously from a first edge of the second molding material to a second edge of the second molding material disposed opposite the first edge.

8. A packaged semiconductor device comprising:
an integrated circuit die;
a first molding material surrounding sidewalls of the integrated circuit die;
a first through-via partially within the first molding material, wherein a first sidewall of the first through-via contacts the first molding material, and wherein a second sidewall of the first through-via is free from the first molding material;
a redistribution layer (RDL) over the integrated circuit die, the first through-via, and the first molding material;
a second molding material over the RDL; and
a conductive layer over the second molding material, the conductive layer extending along sidewalls of the second molding material and the first molding material.

9. The packaged semiconductor device of claim 8 , further comprising a surface mount in the second molding material.

10. The packaged semiconductor device of claim 8 , wherein the conductive layer contacts the second sidewall of the first through-via.

11. The packaged semiconductor device of claim 10 , wherein the RDL comprises a conductive line partially within an insulating material layer, wherein the conductive layer contacts the conductive line.

12. The packaged semiconductor device of claim 8 , wherein the conductive layer is coupled to ground.

13. The packaged semiconductor device of claim 8 , wherein the conductive layer extends continuously from a first sidewall of the second molding material to a second sidewall of the second molding material opposite the first sidewall of the second molding material.

14. The packaged semiconductor device of claim 8 , wherein the conductive layer comprises an aperture exposing a top surface of the second molding material.

15. A semiconductor device comprising:
a first molding material around a plurality of integrated circuit dies and a first through-via;
a redistribution layer (RDL) over the plurality of integrated circuit dies, the first through-via, and the first molding material;
a surface mount device coupled to the RDL;
a second molding material around the surface mount device and over the RDL;
a second through-via extending through the second molding material; and
a conductive material over the second molding material, the conductive material being coupled to the first through-via, and wherein the conductive material contacts a sidewall of the first through-via.

16. The semiconductor device of claim 15 , wherein the conductive material contacts sidewalls of the second molding material, the RDL, and the first molding material.

17. The semiconductor device of claim 15 , wherein the conductive material comprises a T-shaped aperture.

18. The semiconductor device of claim 15 , further comprising:
a third molding material over the conductive material; and
a second conductive material over the third molding material, wherein the conductive material comprises a shield portion of an antenna, and wherein the second conductive material comprises an antenna portion of the antenna.

19. The semiconductor device of claim 18 , wherein the conductive material comprises an aperture.

20. The semiconductor device of claim 15 , wherein the conductive material comprises a continuous sheet covering an entire top surface of the second molding material.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwwan Semiconductor Mfg Company Ltd

Inventors

• Tang Tzu-Chun
• Wang Chuei-Tang
• Lu Chun-Lin
• Chen Wei-Ting
• Chen Vincent
• Chang Shou-Zen
• Wu Kai-Chiang

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W42/267

  Patterned shielding planes · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title