Semiconductor package with terminal pattern for increased channel density

Patent metadata

Field	Value
Publication number	US-11211315-B2
Application number	US-201715784066-A
Country	US
Kind code	B2
Filing date	Oct 13, 2017
Priority date	Oct 13, 2017
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

Described examples include an apparatus, including: a substrate having a first surface configured to mount at least one integrated circuit and having a second surface opposite the first surface, the second surface having a plurality of terminals arranged in rows and columns, and at least one row of the plurality of terminals disposed adjacent a first side and extending generally along the length of the substrate arranged in a pattern extending along a longitudinal line, the pattern including a first group of consecutive terminals extending in a first direction at a first angle to the longitudinal line and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle and extending towards the periphery of the substrate, and a third group of consecutive ones of the terminals extending from the second group in the first direction.

First claim

What is claimed is:

1. An apparatus, comprising:
a substrate having a first surface configured to include at least one integrated circuit, and having a second surface opposite the first surface, the second surface having a plurality of terminals, the substrate having a a first, second, third, and fourth sides forming a periphery of the substrate; and
at least a first set of the plurality of terminals disposed adjacent the first side of the substrate and forming a periphery of the plurality of terminals adjacent to the first side of the substrate, the first set of the plurality of terminals arranged in a pattern, the pattern comprising a first group of consecutive ones of the terminals extending in a first direction at a first angle to a longitudinal line parallel to the first side and directed towards an interior of the substrate, a second group of consecutive terminals extending in a second direction at a second angle with respect to the first direction and extending towards the periphery of the substrate, and a third group of consecutive ones of the of the terminals extending from the second group and extending in the first direction at a third angle to the second direction and away from the periphery of the substrate, wherein the plurality of terminals is electrically connected to the integrated circuit.

2. The apparatus of claim 1 , in which the first angle is an angle of forty five degrees with respect to the longitudinal line.

3. The apparatus of claim 2 , in which the second angle is ninety degrees with respect to the first direction.

4. The apparatus of claim 3 , in which the third angle is an angle of ninety degrees with respect to the second direction.

5. The apparatus of claim 1 , in which the terminals are solder balls.

6. The apparatus of claim 5 , in which the apparatus forms a ball grid array (BGA) package for the integrated circuit.

7. The apparatus of claim 1 , in which the plurality of terminals include signal terminals for at least one of transmitting and receiving communication signals interspersed with ground terminals for coupling to a ground potential.

8. The apparatus of claim 7 in which the signal terminals include pairs of differential signal terminals disposed adjacent one another, the pairs spaced apart by ground terminals.

9. The apparatus of claim 8 in which the pairs of signal terminals are configured to transmit or receive PCI-Express signals.

10. The apparatus of claim 1 , and further including at least one additional terminal placed between the first set of the plurality of terminals and the periphery of the substrate, wherein the at least one additional terminal is not electrically connected to the integrated circuit.

11. The apparatus of claim 1 further comprising:
a second set of the plurality of terminals disposed adjacent the second side of the substrate and forming a periphery of the plurality of terminals adjacent to the second side of the substrate;
a third set of the plurality of terminals disposed adjacent the third side of the substrate and forming a periphery of the plurality of terminals adjacent to the third side of the substrate; and
a fourth set of the plurality of terminals disposed adjacent the fourth side of the substrate and forming a periphery of the plurality of terminals adjacent to the fourth side of the substrate.

12. The apparatus of claim 11 , in which the first set of the plurality of terminals, the second set of the plurality of terminals, the third set of the plurality of terminals, and the fourth set of the plurality of terminals together form a periphery of the plurality of terminals from a bottom view of the apparatus.

Assignees

• Texas Instruments Inc

Inventors

• Morrison Casey Thomas
• Sledjeski Lee Martin

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title