Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-2016172016-A1
Application number	US-201514643339-A
Country	US
Kind code	A1
Filing date	Mar 10, 2015
Priority date	Dec 12, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

According to one embodiment, a semiconductor device includes, for example, a circuit board, a plurality of elements, a plurality of controllers, and a first signal line. The elements are provided on the circuit board. The elements each include a memory. The controllers each are configured to control read of data from the memory. The controllers each are configured to control write of data into the memory. A control signal is transmitted through the first signal line. The first signal line is used in common by the controllers.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a circuit board; a plurality of elements provided on the circuit board, the elements each including a memory; a plurality of controllers each configured to control the memory; and a first signal line through which a control signal is transmitted, the first signal line being used in common by the controllers.

2 . The semiconductor device according to claim 1 , wherein the elements each include one of the controllers, the controllers each being configured to control read of data from the memory included in one of the elements, the controllers each being configured to control write of data into the memory included in one of the elements.

3 . The semiconductor device according to claim 1 , wherein the semiconductor device includes an interface unit configured to be connectable to a host device, wherein
the interface unit includes a first terminal and a second terminal, the first terminal being electrically connected to the first signal line, the second terminal being electrically connected to a second signal line, the second signal line being connected to one or more controllers among the controllers, the second signal line being a line through which a data signal is transmitted.

4 . The semiconductor device according to claim 3 , wherein the interface unit includes a third terminal, and an electric status corresponding to a configuration of the semiconductor device is set in the third terminal.

5 . The semiconductor device according to claim 4 , wherein the electric status is an impedance status.

6 . The semiconductor device according to claim 4 , wherein the electric status is a potential status.

7 . The semiconductor device according to claim 6 , wherein the third terminal is set at a ground potential of the semiconductor device, or set at a potential different from the ground potential and a power supply potential of the semiconductor device.

8 . The semiconductor device according to claim 1 , wherein the circuit board includes a first face, and
the plurality of elements are provided on the first face.

9 . The semiconductor device according to claim 1 , wherein the circuit board includes a first face and a second face, the second face being on a side opposite to the first face, and
a first element among the elements is provided on the first face, a second element among the elements being provided on the second face.

10 . An electronic device comprising:
a host device; and a semiconductor device, the semiconductor device including a circuit board, a plurality of elements, and a first signal line, the memory elements being provided on the circuit board, the memory elements each including a memory and a controller configured to control the memory, the first signal line being a line through which a control signal is transmitted, the first signal line being used in common by a plurality of the controllers.

11 . The electronic device according to claim 10 , wherein the semiconductor device further includes an interface unit configured to be connectable to the host device, wherein the interface unit conforms to PCI Express.

12 . The electronic device according to claim 10 , wherein the semiconductor device further includes an interface unit configured to be connectable to the host device, and the interface unit includes a first terminal and a second terminal, the first terminal being electrically connected to the first signal line, the second terminal being electrically connected to a second signal line, the second signal line being connected to one or more controllers among the controllers, the second signal line being a line through which a data signal is transmitted.

13 . The electronic device according to claim 12 , wherein the interface unit includes a third terminal, and an electric status corresponding to a configuration of the semiconductor device is set in the third terminal.

14 . The electronic device according to claim 13 , wherein the host device is configured to detect the electric status set in the third terminal, and discriminate the configuration of the semiconductor device based on the detected electric status.

15 . The electronic device according to claim 14 , wherein the host device is configured to construct a RAID using the elements based on the detected electric status.

16 . The electronic device according to claim 15 , wherein the electric status is an impedance status.

17 . The electronic device according to claim 15 , wherein the electric status is a potential status.

18 . The electronic device according to claim 17 , wherein the third terminal is set at a ground potential of the semiconductor device, or set at a potential different from the ground potential and a power supply potential of the semiconductor device.

19 . The electronic device according to claim 10 , wherein the circuit board includes a first face, and
the elements are provided on the first face.

20 . The electronic device according to claim 10 , wherein the circuit board includes a first face and a second face, the second face being on a side opposite to the first face, and
a first element among the elements is provided on the first face, a second element among the elements being provided on the second face.

Assignees

• Toshiba Kk

Inventors

• Matsumoto Manabu
• Murakami Katsuya
• Nagai Koichi

Classifications

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title