Memory system with single decoder, multiple memory sets and method for decoding multiple codewords from memory sets using the single decoder
US-2021249080-A1 · Aug 12, 2021 · US
Semiconductor device
US11211123B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11211123-B2 |
| Application number | US-201816769663-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 30, 2018 |
| Priority date | Dec 11, 2017 |
| Publication date | Dec 28, 2021 |
| Grant date | Dec 28, 2021 |
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- Title
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Abstract
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A disclosed semiconductor device includes a memory cell with a first terminal, a second terminal, a memory element having a first resistance state and a second resistance state, and a nonlinear element, and a drive controller that performs a first operation that allows the memory element to be in the first resistance state, a second operation that allows the memory element to be in the second resistance state, a third operation in which the voltage of the first and second terminals is caused to be different from each other and a value of electric current flowing between the first terminal and the second terminal is caused to be limited to a first current value to determine the resistance state, and a fourth operation in which the current value is caused to be limited to a second current value. The drive controller performs the fourth operation after at least one of the first to third operations.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a memory cell that includes a first terminal, a second terminal, a memory element configured to take a first resistance state and a second resistance state, and a nonlinear element configured to be in an on-state when a voltage difference between both ends is larger than a predetermined voltage difference, the memory element and the nonlinear element being provided on a path between the first terminal and the second terminal; and a drive controller that performs a first operation in which a first voltage of the first terminal is caused to be higher than a second voltage of the second terminal to allow a resistance state of the memory element to be in the first resistance state, a second operation in which the first voltage is caused to be lower than the second voltage to allow the resistance state of the memory element to be in the second resistance state, a third operation in which the first voltage and the second voltage are caused to be different from each other and a current value of electric current flowing between the first terminal and the second terminal is caused to be limited to lower than or equal to a first current value to determine the resistance state of the memory element, and a fourth operation in which the first voltage and the second voltage are caused to be different from each other and the current value is caused to be limited to lower than or equal to a second current value, wherein the drive controller performs the fourth operation after at least one of the first operation, the second operation, or the third operation, and wherein the nonlinear element includes a material containing a chalcogen element. 2. The semiconductor device according to claim 1 , wherein the drive controller performs the fourth operation after the first operation. 3. The semiconductor device according to claim 1 , wherein the drive controller performs the fourth operation after the second operation. 4. The semiconductor device according to claim 1 , wherein the drive controller performs the fourth operation after the third operation. 5. The semiconductor device according to claim 1 , wherein the drive controller consecutively performs the fourth operation immediately after at least one of the first operation, the second operation, or the third operation. 6. A semiconductor device, comprising: a memory cell that includes a first terminal, a second terminal, a memory element configured to take a first resistance state and a second resistance state, and a nonlinear element configured to be in an on-state when a voltage difference between both ends is larger than a predetermined voltage difference, the memory element and the nonlinear element being provided on a path between the first terminal and the second terminal; and a drive controller that performs a first operation in which a first voltage of the first terminal is caused to be higher than a second voltage of the second terminal to allow a resistance state of the memory element to be in the first resistance state, a second operation in which the first voltage is caused to be lower than the second voltage to allow the resistance state of the memory element to be in the second resistance state, a third operation in which the first voltage and the second voltage are caused to be different from each other and a current value of electric current flowing between the first terminal and the second terminal is caused to be limited to lower than or equal to a first current value to determine the resistance state of the memory element, and a fourth operation in which the first voltage and the second voltage are caused to be different from each other and the current value is caused to be limited to lower than or equal to a second current value, wherein the drive controller performs the fourth operation after at least one of the first operation, the second operation, or the third operation, and wherein the drive controller performs, after the fourth operation, any one of the first operation, the second operation, and the third operation. 7. The semiconductor device according to claim 6 , wherein the drive controller consecutively performs, immediately after the fourth operation, any one of the first operation, the second operation, and the third operation. 8. The semiconductor device according to claim 1 , wherein the second current value is a current value lower than or equal to the first current value. 9. A semiconductor device, comprising: a memory cell that includes a first terminal, a second terminal, a memory element configured to take a first resistance state and a second resistance state, and a nonlinear element configured to be in an on-state when a voltage difference between both ends is larger than a predetermined voltage difference, the memory element and the nonlinear element being provided on a path between the first terminal and the second terminal; and a drive controller that performs a first operation in which a first voltage of the first terminal is caused to be higher than a second voltage of the second terminal to allow a resistance state of the memory element to be in the first resistance state, a second operation in which the first voltage is caused to be lower than the second voltage to allow the resistance state of the memory element to be in the second resistance state, a third operation in which the first voltage and the second voltage are caused to be different from each other and a current value of electric current flowing between the first terminal and the second terminal is caused to be limited to lower than or equal to a first current value to determine the resistance state of the memory element, and a fourth operation in which the first voltage and the second voltage are caused to be different from each other and the current value is caused to be limited to lower than or equal to a second current value, wherein the drive controller performs the fourth operation after at least one of the first operation, the second operation, or the third operation, and wherein the drive controller causes, in the third operation, the first voltage to be higher than the second voltage. 10. A semiconductor device, comprising: a memory cell that includes a first terminal, a second terminal, a memory element configured to take a first resistance state and a second resistance state, and a nonlinear element configured to be in an on-state when a voltage difference between both ends is larger than a predetermined voltage difference, the memory element and the nonlinear element being provided on a path between the first terminal and the second terminal; and a drive controller that performs a first operation in which a first voltage of the first terminal is caused to be higher than a second voltage of the second terminal to allow a resistance state of the memory element to be in the first resistance state, a second operation in which the first voltage is caused to be lower than the second voltage to allow the resistance state of the memory element to be in the second resistance state, a third operation in which the first voltage and the second voltage are caused to be different from each other and a current value of electric current flowing between the first terminal and the second terminal is caused to be limited to lower than or equal to a first current value to determine the resistance state of the memory element, and a fourth operation in which the first voltage and the second voltage are caused to be different from each other and the current value is caused to be limited to lower than or equal to a second current value, wherein the drive controller performs the fourth operation after at least one of the first operatio
Assignees
Inventors
Classifications
Power supply circuits · CPC title
Bit-line or column circuits · CPC title
Read using current through the cell · CPC title
- G11C13/0069Primary
Writing or programming circuits or methods · CPC title
Reading or sensing circuits or methods · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US11211123B2 cover?
- A disclosed semiconductor device includes a memory cell with a first terminal, a second terminal, a memory element having a first resistance state and a second resistance state, and a nonlinear element, and a drive controller that performs a first operation that allows the memory element to be in the first resistance state, a second operation that allows the memory element to be in the second r…
- Who is the assignee on this patent?
- Sony Semiconductor Solutions Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C13/0069. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 28 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).