Speculative buffer for speculative memory accesses with entries tagged with execution context identifiers

Patent metadata

Field	Value
Publication number	US-11210102-B2
Application number	US-201916695735-A
Country	US
Kind code	B2
Filing date	Nov 26, 2019
Priority date	Nov 26, 2019
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

An apparatus comprises processing circuitry to execute instructions from one or more of a plurality of execution contexts each associated with a respective execution context identifier; a cache; and a speculative buffer. Control circuitry controls allocation of data to the cache and the speculative buffer. A speculative entry, for which allocation is caused by a speculative memory access associated with a given execution context, is allocated to the speculative buffer instead of to the cache while the speculatively executed memory access instruction remains speculative. The speculative entry specifies, as a tagged execution context identifier, the execution context identifier associated with the given execution context. Presence of the speculative entry in the speculative buffer is prevented from being observable to execution contexts other than the execution context identified by the tagged execution context identifier.

First claim

The invention claimed is:

1. An apparatus comprising:
processing circuitry to execute instructions from one or more of a plurality of execution contexts each associated with a respective execution context identifier;
a cache;
a speculative buffer; and
control circuitry to control allocation of data to the cache and the speculative buffer; in which:
the control circuitry is configured to allocate a speculative entry, for which allocation is caused by a speculative memory access associated with a given execution context, to the speculative buffer instead of to the cache while the speculative memory access remains speculative, the speculative entry in the speculative buffer specifying, as a tagged execution context identifier, the execution context identifier associated with the given execution context; and
the control circuitry is configured to prevent presence of the speculative entry in the speculative buffer being observable to an execution context other than the given execution context identified by the tagged execution context identifier specified by the speculative entry; and
in response to a speculative memory access request received from a requester, the speculative memory access request specifying a target address and a target execution context identifier identifying an execution context associated with the speculative memory access request, the control circuitry is configured to perform a cache lookup in the cache based on the target address, and to perform a speculative buffer lookup in the speculative buffer based on the target address and the target execution context identifier; and
in response to both the cache lookup identifying a cache miss and the speculative buffer lookup identifying that the speculative buffer comprises an existing speculative entry corresponding to the target address for which there is a mismatch between the tagged execution context identifier and the target execution context identifier:
the control circuitry is configured to issue a request to trigger eviction, from another speculative buffer associated with at least one other cache, of a speculative entry corresponding to the target address and the tagged execution context identifier of the existing speculative entry.

2. The apparatus according to claim 1 , in which the control circuitry is configured to exclusively allocate, to the cache, cache entries corresponding to non-speculative memory accesses or speculative memory accesses which have already been resolved as correct.

3. The apparatus according to claim 1 , in which the control circuitry is configured to permit presence of a cache entry in the cache to be observable to an execution context other than the given execution context.

4. The apparatus according to claim 1 , comprising at least two levels of cache, each of said at least two levels of cache associated with a corresponding speculative buffer to store a speculatively allocated entry for transferring to the corresponding level of cache after a speculative memory access which caused allocation of the speculatively allocated entry has been resolved as correct.

5. The apparatus according to claim 4 , in which when issuing a further request to a downstream cache or memory as a response to a request received from the processing circuitry or an upstream cache specifying a given execution context identifier, the control circuitry is configured to issue the further request to the downstream cache or memory specifying the given execution context identifier.

6. The apparatus according to claim 1 , in which the execution context identifier associated with the given execution context comprises a function of at least one of:
a processor core identifier identifying a processor core on which the given execution context is executed;
a hardware thread identifier identifying a hardware thread corresponding to the given execution context;
a virtual machine identifier identifying a virtual machine associated with the given execution context;
an address translation context identifier identifying an address translation context associated with the given execution context; and
a program instruction address of an instruction which started execution of a speculative block of instructions from the given execution context.

7. The apparatus according to claim 1 , in which the cache is a shared cache shared between a plurality of processor cores, and the speculative buffer is accessible in response to requests issued by any of the plurality of processor cores.

8. The apparatus according to claim 1 , in which the processing circuitry is configured to execute a plurality of hardware threads each associated with a respective hardware thread identifier, the execution context identifier associated with the given execution context is dependent on the hardware thread identifier of the hardware thread in which the given execution context is executed, and the speculative buffer is accessible to any of said hardware threads.

9. The apparatus according to claim 1 , in which the speculative memory access associated with the given execution context is at least one of:
an instruction-triggered memory access issued in response to a speculatively executed memory access instruction of the given execution context; and
a prefetch-triggered memory access issued by a prefetcher.

10. The apparatus according to claim 1 , in which the control circuitry is configured to allocate the speculative entry to the speculative buffer in response to a speculative read request to request reading of data associated with a target address.

11. The apparatus according to claim 1 , in which when the cache lookup identifies a cache miss, and the speculative buffer lookup identifies that the speculative buffer comprises an existing speculative entry corresponding to the target address for which the tagged execution context identifier matches the target execution context identifier, the control circuitry is configured to service the speculative memory access request using data stored in the speculative buffer in the existing speculative entry corresponding to the target address for which the tagged execution context identifier matches the target execution context identifier.

12. The apparatus according to claim 1 , in which when the cache lookup identifies a cache miss, and the speculative buffer lookup identifies that the speculative buffer comprises the existing speculative entry corresponding to the target address for which there is a mismatch between the tagged execution context identifier and the target execution context identifier, the control circuitry is configured to service the speculative memory access request with a delay corresponding to a miss delay incurred when the speculative memory access request misses in both the cache and the speculative buffer.

13. The apparatus according to claim 12 , in which the control circuitry is configured to service the speculative memory access request with the delay corresponding to the miss delay by one of:
returning a response to the requester based on the existing speculative entry after a simulated delay simulating the miss delay, while the existing speculative entry remains valid in the speculative buffer; and
triggering eviction of the existing speculative entry, and issuing a linefill request to a downstream cache or memory to request re-fetching of data associated with the existing speculative entry.

14. The apparatus according to claim 1 , in which in response to a speculative-promote request specifying a target address, when the speculative buffer comprises a given speculative entry corresponding to the target address specified by the specul

Assignees

• Advanced Risc Mach Ltd

Inventors

• Grubisic Roko

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3842 Primary

  Speculative instruction execution · CPC title

• G06F9/3832 Primary

  Value prediction for operands; operand history buffers · CPC title

• G06F9/30123

  according to context, e.g. thread buffers · CPC title

• G06F12/1045

  associated with a data cache · CPC title