Secure speculative instruction execution in a data processing system

Patent metadata

Field	Value
Publication number	US-2019310941-A1
Application number	US-201815945047-A
Country	US
Kind code	A1
Filing date	Apr 4, 2018
Priority date	Apr 4, 2018
Publication date	Oct 10, 2019
Grant date	—

Abstract

A data processing system includes a processor, a cache memory, a speculative cache memory, and a control circuit. The processor is for executing instructions. The cache memory is coupled to the processor and is for storing the instructions and related data. A speculative cache is coupled to the processor and is for storing only speculative instructions and related data. The control circuit is coupled to the processor, to the cache memory, and to the speculative cache. The control circuit is for causing speculative instructions to be stored in the speculative cache in response to receiving an indication from the processor. Also, a method is provided for speculative execution in the data processing system.

First claim

What is claimed is:

1 . A method for speculative execution in a data processing system, the method comprising:
receiving an instruction to be executed by a processor of the data processing system, wherein the instruction is for accessing a memory for reading or writing data according to the instruction; determining that the access is speculative; determining that the data is not in a cache memory of the data processing system; retrieving the data from a main memory; storing the data in a speculative cache, wherein the speculative cache is for storing only speculative instructions and data related to the speculative instructions; and executing the speculative instruction.

2 . The method of claim 1 , wherein accessing a memory for reading or writing further comprises accessing the memory for reading data, and further comprising transferring the data to a register.

3 . The method of claim 1 , wherein accessing a memory for reading or writing further comprises accessing the memory for writing data, and further comprising overwriting the data in the speculative cache by new data from a register.

4 . The method of claim 1 , further comprising retiring the speculative instruction.

5 . The method of claim 1 , further comprising:
retiring the speculative instruction; determining that there are changes to the speculative cache; and transferring data from the speculative cache to the cache memory.

6 . The method of claim 1 , wherein accessing a memory for reading or writing further comprises accessing the memory for reading data, and wherein determining that the data is not in a cache memory further comprises determining that the data is no the cache memory or the speculative cache.

7 . The method of claim 1 , further comprising preventing write operations to the cache memory during the speculative execution.

8 . A data processing system comprising:
a processor for executing instructions; a cache memory, coupled to the processor, for storing the instructions and related data; a speculative cache, coupled to the processor, for storing only speculative instructions and related data; and a control circuit, coupled to the processor, to the cache memory, and to the speculative cache, the control circuit for causing the speculative instructions to be stored in the speculative cache in response to receiving an indication from the processor.

9 . The data processing system of claim 8 , wherein the processor further comprises a branch predictor, wherein speculative execution is performed in response to a prediction from the branch predictor regarding a speculative instruction.

10 . The data processing system of claim 9 , wherein an instruction retirement circuit of the processor retires the speculative instruction in response to the prediction being determined to be correct.

11 . The data processing system of claim 8 , wherein speculative cache and the cache memory are separate portions of the same memory array.

12 . The data processing system of claim 8 , wherein the processor further comprises an instruction retirement circuit for retiring a speculative instruction after the speculative instruction is executed.

13 . The data processing system of claim 8 , wherein the control circuit prevents write operations to the cache memory during the speculative execution and only allows write operations to the speculative cache during the speculative execution.

14 . A method for speculative execution in a data processing system, the method comprising:
receiving an instruction to be executed by the processor, wherein the instruction is for accessing a memory for reading or writing data according to the instruction; determining that the access is speculative; preventing write operations to the cache memory during the speculative execution; determining that the data is not in a cache memory of the data processing system; retrieving the data from a main memory; storing the data in a speculative cache, wherein the speculative cache is for storing only speculative instructions and data related to the speculative instructions; and executing the speculative instruction.

15 . The method of claim 14 , wherein the instruction is for a read access, and wherein the data is transferred to a register of the processor.

16 . The method of claim 14 , wherein the instruction is for a write access for writing data from a register of the processor to the speculative cache, and further comprising overwriting data in the speculative cache with the data from the register, and marking the data in the speculative cache as dirty.

17 . The method of claim 14 , further comprising retiring the speculative instruction.

18 . The method of claim 17 , further comprising:
determining that there are changes to the data in the speculative cache; and transferring data from the speculative cache to the cache memory.

19 . The method of claim 14 , wherein accessing a memory for reading or writing further comprises accessing the memory for reading data, and wherein determining that the data is not in a cache memory further comprises determining that the data is not in the cache memory or the speculative cache.

20 . The method of claim 14 , wherein determining that the data is not in a cache memory further comprises determining that the data is not in the cache memory or the speculative cache.

Assignees

• Nxp Bv

Inventors

• Veshchikov Nikita

Classifications

• G06F9/3824

  Operand accessing · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title

• G06F2212/507

  using speculative control · CPC title

• G06F12/0844 Primary

  Multiple simultaneous or quasi-simultaneous cache accessing · CPC title

• G06F9/3842 Primary

  Speculative instruction execution · CPC title