Coreless organic packages with embedded die and magnetic inductor structures

Patent metadata

Field	Value
Publication number	US-11205626-B2
Application number	US-202016875417-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	Aug 31, 2018
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

First claim

We claim:

1. A coreless semiconductor package comprising:
plurality of dielectric layers;
a magnetic inductor at least partly embedded within a first group of the plurality of layers;
an embedded multi-die interconnect bridge (EMIB) adjacent the magnetic inductor, the EMIB embedded within a second group of the plurality of layers;
a plurality of vias and interconnections in the plurality of layers, configured to connect a die of the EMIB to other circuitry;
a first level interconnect (FLI) on a first side of the package, the FLI configured to connect to at least some of the plurality of vias and interconnections; and
a plurality of ball grid array (BGA) pockets and conductive BGA pads on a second side of the package opposite the first side of the package.

2. The coreless semiconductor package of claim 1 wherein the magnetic inductor comprises a plurality of conductive traces encapsulated by magnetic material.

3. The coreless semiconductor package of claim 2 wherein the magnetic material comprises two different types of magnetic materials.

4. The coreless semiconductor package of claim 1 wherein the plurality of BGA pads comprises plated copper.

5. The coreless semiconductor package of claim 1 wherein the FLI comprises copper, copper-gold-palladium-silver, copper-nickel-silver, copper-tin, or copper-nickel-tin.

6. The coreless semiconductor package of claim 2 further comprising an organic solderability preservative deposited on at least some of the conductive BGA pads.

7. The coreless semiconductor package of claim 1 further comprising a conductive laser stop plated on a BU layer adjacent the magnetic inductor, the conductive laser stop configured to protect the magnetic inductor from chemistry process steps that are performed on at least some of the plurality of layers.

8. An electronic device comprising:
one or more processor cores;
memory; and
a memory controller, wherein
at least one of the one or more processor cores, memory, or memory controller includes a coreless semiconductor package comprising:
a plurality of dielectric layers;
a magnetic inductor at least partly embedded within a first group of the plurality of layers;
an embedded multi-die interconnect bridge (EMIB) adjacent the magnetic inductor, the EMIB embedded within a second group of the plurality of layers;
a plurality of vias and interconnections in the plurality of layers, configured to connect a die of the EMIB to other circuitry;
a first level interconnect (FLI) on a first side of the package, the FLI configured to connect to at least some of the plurality of vias and interconnections; and

a plurality of ball grid array (BGA) pockets and conductive BGA pads on a second side of the package opposite the first side of the package.

9. The electronic device of claim 8 wherein the magnetic inductor comprises a plurality of conductive traces encapsulated in magnetic material.

10. The electronic device of claim 9 wherein the magnetic material comprises two different types of magnetic materials.

11. The electronic device of claim 8 the method further comprising plating a conductive laser stop on a BU layer adjacent the magnetic inductor.

12. The electronic device of claim 9 wherein the FLI comprises copper, copper-gold-palladium-silver, copper-nickel-silver, copper-tin, or copper-nickel-tin.

13. The electronic device of claim 8 further comprising an organic solderability preservative deposited on at least some of the conductive BGA pads.

14. A method of forming a coreless semiconductor package, the method comprising:
providing a peelable core;
forming, by using a photolithographic process, a coreless plurality of multi-element conductive layers on the peelable core, the multi-element conductive layers formed in a pattern of a BGA;
forming on the plurality of multi-element convictive layers a plurality of dielectric layers;
embedding a first magnetic material at least partly within a first group of the plurality of layers;
embedding an EMIB adjacent the first magnetic material, the EMIB embedded within a second group of the plurality of layers;
forming in the plurality of layers a plurality of vias and interconnections configured to connect a die of the EMIB to other circuitry;
forming an FLI on a first side of the package, the FLI configured to connect to at least some of the plurality of vias and interconnections;
depaneling the peelable core; and
forming from the plurality of multi-element conductive layers a plurality of pockets and conductive pads on a second side of the package opposite the first side of the package.

15. The method of claim 14 further comprising:
enveloping a plurality of conductive traces with a second magnetic material wherein each of the conductive traces comprises a conductive pad adjacent the first magnetic material, wherein the conductive traces are encapsulated by the first magnetic material and the second magnetic material to form an inductor.

16. The method of claim 15 wherein the first magnetic material and the second magnetic material each comprises a different type of magnetic material.

17. The method of claim 14 wherein solder balls are placed in contact with conductive pads within at least some of the pockets.

18. The method of claim 15 further comprising depositing an organic solderability preservative on at least some of the conductive pads.

19. The method of claim 14 wherein forming an FLI on a first side of the package comprises forming a solder resist (SR) layer on the first side of the package, forming SR openings (SROs) in the SR and forming the FLI in the SROs.

20. The method of claim 14 wherein embedding a first magnetic material at least partly within a first group of the plurality of layers comprises drilling a cavity in at least one of the first group of the plurality of layers, depositing a protective magnetic layer in the cavity, and laminating at least one BU film to fill the cavity.

21. The method of claim 20 further comprising plating a laser stop on the BU film that fills the cavity.

22. A method of forming a plurality of coreless semiconductor packages, the method comprising:
providing a peelable core;
forming, on the peelable core, by using a photolithographic process, a plurality of multi-element conductive layers on one of the plurality of layers, the multi-element conductive layers formed in a pattern of a BGA;
forming on the plurality of multi-element conductive layers a plurality of dielectric layers, by a method comprising:
embedding a plurality of a first magnetic material at least partly within a first group of the plurality of layers of dielectric material;
depaneling the peelable core;
forming from the plurality of multi-element conductive layers a plurality of pockets and conductive pads on a second side of the package opposite a first side of the plurality of layers of dielectric material;
attaching a carrier;
embedding a plurality of EMIBs adjacent respective ones of the first magnetic materials, each EMIB embedded within a second group of the plurality of layers of dielectric material;
forming, in the plurality of layers of dielectric material, respective vias and interconnections configured to connect a die of respective ones of the EMIB to other circuitry;
forming respective FLIs on the first side of the plurality of layers of dielectric material opposite the second side of the plurality of layers, the FLI configured to connect to at least some of the respective vias and intercon

Assignees

• Intel Corp

Inventors

• Brown Andrew J
• Jain Rahul
• Chatterjee Prithwish
• Link Lauren A
• Vadlamani Sai

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title