Secure crypto module including optical security pathway

US11205016B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11205016-B2
Application numberUS-201916426705-A
CountryUS
Kind codeB2
Filing dateMay 30, 2019
Priority dateMar 24, 2016
Publication dateDec 21, 2021
Grant dateDec 21, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An optical electromagnetic radiation (EM) emitter and receiver are located upon a printed circuit board (PCB) layer and are optically connected to an optical security pathway that is between a pair of signal traces. A predetermined reference flux is determined, the reference flux being the expected EM transmitted by the optical security pathway and received by the receiver. When the PCB is subject to an unauthorized access thereof (e.g., drilled, sawed, cut, etc.), the optical EM transferred by optical security pathway is altered. An optical monitoring device that monitors the flux of the optical EM received by the receiver detects a change in flux, in relation to the reference flux, and passes a tamper signal to one or more computer system devices to respond to the unauthorized access. For example, one or more cryptographic adapter card or computer system functions or secured crypto components may be disabled.

First claim

Opening claim text (preview).

What is claimed is: 1. A cryptographic adapter card comprising: a printed circuit board (PCB) comprising a connector that interconnects with a motherboard; a secure crypto module comprising a daughter card electrically connected to the PCB; the daughter card comprising: a wiring dielectric layer, a pair of neighboring signal traces upon the wiring dielectric layer, an optical waveguide upon the wiring dielectric layer between and contacting the pair of neighboring signal traces, an optical electromagnetic radiation (EM) emitter upon the wiring dielectric layer optically connected to a first end of the optical waveguide, an optical EM receiver upon the wiring dielectric layer optically connected to a second end of the optical waveguide, and a crypto component; wherein a destruct feature of the crypto component is programmed in response to the optical EM receiver detecting a predetermined threshold decrease in optical flux of optical EM that is emitted from the optical EM emitter, that is transmitted by the optical waveguide, and that is received at the optical EM receiver. 2. The cryptographic adapter card of claim 1 , wherein the pair of neighboring signal traces comprises a first conductive signal trace directly upon the wiring dielectric layer and a second conductive signal trace directly upon the wiring dielectric layer. 3. The cryptographic adapter card of claim 2 , wherein a first sidewall of the optical waveguide contacts the first conductive signal trace and a second sidewall of the optical waveguide contacts the second conductive signal trace. 4. The cryptographic adapter card of claim 1 , wherein the daughter card further comprises an optical monitor device that generates a tamper signal in response to the optical EM receiver detecting the predetermined threshold decrease in optical flux. 5. The cryptographic adapter card of claim 4 , wherein the daughter card further comprises an enable device that upon receipt of the tamper signal from the monitor device programs the destruct feature. 6. The cryptographic adapter card of claim 1 , wherein the optical waveguide comprises a core surrounded by a cladding layer. 7. The cryptographic adapter card of claim 1 , wherein the daughter card further comprises an optically opaque encapsulation layer upon the transparent dielectric layer. 8. The cryptographic adapter card of claim 1 , wherein the optical EM receiver detects the predetermined threshold decrease in optical flux as a result of a void that intersects the optical waveguide. 9. A data handling electronic device comprising: a motherboard comprising a processor and a memory; a cryptographic adapter card connected to the motherboard, the cryptographic adapter card comprising: a printed circuit board (PCB) comprising a connector that interconnects with the motherboard; a secure crypto module comprising a daughter card electrically connected to the PCB; the daughter card comprising: a wiring dielectric layer, a pair of neighboring signal traces upon the wiring dielectric layer, an optical waveguide upon the wiring dielectric layer between and contacting the pair of neighboring signal traces, an optical electromagnetic radiation (EM) emitter upon the wiring dielectric layer optically connected to a first end of the optical waveguide, an optical EM receiver upon the wiring dielectric layer optically connected to a second end of the optical waveguide, and a crypto component; wherein a destruct feature of the crypto component is programmed in response to the optical EM receiver detecting a predetermined threshold decrease in optical flux of optical EM that is emitted from the optical EM emitter, that is transmitted by the optical waveguide, and that is received at the optical EM receiver. 10. The data handling electronic device of claim 9 , wherein the pair of neighboring signal traces comprises a first conductive signal trace directly upon the wiring dielectric layer and a second conductive signal trace directly upon the wiring dielectric layer. 11. The data handling electronic device of claim 10 , wherein a first sidewall of the optical waveguide contacts the first conductive signal trace and a second sidewall of the optical waveguide contacts the second conductive signal trace. 12. The data handling electronic device of claim 9 , wherein the daughter card further comprises an optical monitor device that generates a tamper signal in response to the optical EM receiver detecting the predetermined threshold decrease in optical flux. 13. The data handling electronic device of claim 12 , wherein the daughter card further comprises an enable device that upon receipt of the tamper signal from the monitor device programs the destruct feature. 14. The data handling electronic device of claim 9 , wherein the optical waveguide comprises a core surrounded by a cladding layer. 15. The data handling electronic device of claim 9 , wherein the daughter card further comprises an optically opaque encapsulation layer upon the transparent dielectric layer. 16. The data handling electronic device of claim 9 , wherein the optical EM receiver detects the predetermined threshold decrease in optical flux as a result of a void that intersects the optical waveguide.

Assignees

Inventors

Classifications

  • G06F21/72Primary

    in cryptographic circuits · CPC title

  • Protection from unauthorised access, e.g. eavesdrop protection · CPC title

  • by inhibiting the analysis of circuitry or operation · CPC title

  • Secure or tamper-resistant housings · CPC title

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Frequently asked questions

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What does patent US11205016B2 cover?
An optical electromagnetic radiation (EM) emitter and receiver are located upon a printed circuit board (PCB) layer and are optically connected to an optical security pathway that is between a pair of signal traces. A predetermined reference flux is determined, the reference flux being the expected EM transmitted by the optical security pathway and received by the receiver. When the PCB is subj…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F21/72. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 21 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).