Systems and methods for coherent power management

Patent metadata

Field	Value
Publication number	US-11204636-B2
Application number	US-201916519347-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Feb 13, 2017
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g. with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

First claim

What is claimed is:

1. A system comprising:
a power-managed load comprising a processor;
a power management unit coupled to the power-managed load and configured to supply power to the power-managed load;
a plurality of circuits wherein:
respective circuits of the plurality of circuits implement different power management mechanisms;
the different power management mechanisms affect the same power-managed load;
the plurality of circuits operate in different ones of a plurality of time domains and the plurality of circuits operate concurrently and independently, wherein a time characteristic corresponding to a respective time domain of the plurality of time domains differs from the time characteristic of other ones of the plurality of time domains; and

a control circuit configured to coordinate the power management mechanisms implemented by the plurality of circuits when the power management mechanisms are reacting to a same variation in the power to the power-managed load.

2. The system as recited in claim 1 wherein the power-managed load comprises one or more integrated circuits.

3. The system as recited in claim 1 wherein the power-managed load comprises one or more processors.

4. The system as recited in claim 1 wherein a first power management mechanism of the plurality of power management mechanisms is a fixed phase mode in which the power management unit is configured to limit a number of enabled phases of a voltage regulator in the power management unit to a fixed number.

5. The system as recited in claim 1 wherein a first power management mechanism of the plurality of power management mechanisms is a mode in which the power management unit is configured to disable power to the power-managed load and the power-managed load is configured to operate on energy stored in capacitors coupled between a power supply input to the power-managed load and ground.

6. The system as recited in claim 1 wherein a first power management mechanism of the plurality of power management mechanisms is a dynamic load line mode in which a load line of the power management unit is adjusted during operation based on a state of the power-managed load.

7. The system as recited in claim 1 wherein the time characteristic is a bandwidth.

8. The system as recited in claim 1 wherein the time characteristic is a latency.

9. The system as recited in claim 1 wherein the time characteristics for the plurality of time domains differ from each other by one or more orders of magnitude.

10. The system as recited in claim 1 wherein the time characteristic corresponding to a first time domain of the plurality of time domains in which a first circuit of the plurality of circuits operates is an indication of how quickly the first circuit responds to inputs to generate compensation outputs.

11. A method comprising:
controlling power to a power-managed load using a plurality of circuits, wherein respective circuits of the plurality of circuits implement different power management mechanisms that affect the power-managed load, and wherein the plurality of circuits operate in different ones of a plurality of time domains and the plurality of circuits operate concurrently and independently, wherein a time characteristic corresponding to a respective time domain of the plurality of time domains differs from the time characteristic of other ones of the plurality of time domains; and
coordinating operation of the plurality of circuits when the plurality of circuits are reacting to a same variation in the power to the power-managed load.

12. The method as recited in claim 11 wherein time characteristics associated with the time domains differ by one or more orders of magnitude.

13. The method as recited in claim 11 wherein the time characteristic corresponding to a first time domain of the plurality of time domains in which a first circuit of the plurality of circuits operates is an indication of how quickly the first circuit responds to inputs to generate compensation outputs.

14. The method as recited in claim 11 wherein the power-managed load comprises one or more processors.

15. A system comprising:
a power-managed load;
a plurality of circuits coupled to the power-managed load, wherein:
respective circuits of the plurality of circuits implement different power management mechanisms;
the different power management mechanisms affect the same power-managed load;
the plurality of circuits operate in different ones of a plurality of time domains and the plurality of circuits operate concurrently and independently, wherein a time characteristic corresponding to a respective time domain of the plurality of time domains differs from the time characteristic of other ones of the plurality of time domains and indicates how quickly a respective circuit of the plurality of circuits operating in the respective time domain reacts to inputs to produce compensation outputs; and

a control circuit coupled to the plurality of circuits and configured to coordinate the power management mechanisms implemented by the plurality of circuits when the power management mechanisms are reacting to a same variation in the power to the power-managed load.

16. The system as recited in claim 15 wherein the power-managed load comprises one or more integrated circuits.

17. The system as recited in claim 15 wherein the power-managed load comprises one or more processors.

18. The system as recited in claim 15 wherein the time characteristic is a bandwidth.

19. The system as recited in claim 15 wherein the time characteristic is a latency.

20. The system as recited in claim 15 wherein the time characteristics for the plurality of time domains differ from each other by one or more orders of magnitude.

Assignees

• Apple Inc

Inventors

• Dibene Ii Joseph T
• Sodhi Inder M
• Cox Keith
• Williams Iii Gerard R

Classifications

• G06F1/3203 Primary

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title