Circuit device, physical quantity measurement device, electronic apparatus, and vehicle

Patent metadata

Field	Value
Publication number	US-11201624-B2
Application number	US-202017029203-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 24, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result.

First claim

What is claimed is:

1. A circuit device comprising:
a clock generation circuit configured to generate a first clock signal and a second clock signal different in frequency from the first clock signal;
a signal generation circuit configured to generate a first signal making a transition at a transition timing of the first clock signal, a fine-judging signal making a transition at a transition timing of the second clock signal, a first coarse-judging signal making a transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making a transition at a transition timing of the second clock signal posterior to the fine-judging signal;
a phase comparison circuit configured to perform a phase comparison between a second signal making a transition based on the first signal and the fine-judging signal to thereby output a first phase comparison signal, perform a phase comparison between the second signal and the first coarse-judging signal to thereby output a second phase comparison signal, and perform a phase comparison between the second signal and the second coarse-judging signal to thereby output a third phase comparison signal; and
a processing circuit configured to set a transition timing of the first signal and a transition timing of the fine-judging signal based on the first phase comparison signal, the second phase comparison signal, and the third phase comparison signal, and then convert a time difference between the first signal and the second signal into a digital value based on a result of the setting.

2. The circuit device according to claim 1 , wherein
the signal generation circuit changes the transition timing of the first signal and the transition timing of the fine-judging signal based on the first phase comparison signal when the second phase comparison signal and the third phase comparison signal are in opposite signal levels, and changes the transition timing of the fine-judging signal when the second phase comparison signal and the third phase comparison signal are in a same signal level.

3. The circuit device according to claim 2 , wherein
the signal generation circuit changes the transition timing of the first clock signal for making the transition of the first signal and the transition timing of the second clock signal for making the transition of the fine-judging signal as much as a same clock count when the second phase comparison signal and the third phase comparison signal are in the opposite signal levels, and changes the transition timing of the first clock signal for making the transition of the first signal and the transition timing of the second clock signal for making the transition of the fine-judging signal as much as respective clock counts different from each other when the second phase comparison signal and the third phase comparison signal are in the same signal level.

4. The circuit device according to claim 1 further comprising:
a register configured to store a first clock count and a second clock count, wherein
the signal generation circuit makes the transition of the first signal at a transition timing in the first clock count of the first clock signal from a synchronizing timing at which the first clock signal and the second clock signal coincide in phase with each other, and makes the transition of the fine-judging signal at a transition timing in a clock count obtained by adding the first clock count and the second clock count to each other of the second clock signal from the synchronizing timing, and
the processing circuit updates the first clock count and the second clock count to be stored in the register based on the first phase comparison signal, the second phase comparison signal and the third phase comparison signal.

5. The circuit device according to claim 4 , wherein
when the second phase comparison signal and the third phase comparison signal are in the opposite signal levels, the processing circuit updates the first clock count based on the first phase comparison signal while keeping the second clock count, and the signal generation circuit changes the transition timing of the first signal and the transition timing of the fine-judging signal based on the first clock count updated by the processing circuit and the second clock count kept, and
when the second phase comparison signal and the third phase comparison signal are in the same signal level, the processing circuit keeps the first clock count while updating the second clock count, and the signal generation circuit changes the transition timing of the fine-judging signal without changing the transition timing of the first signal based on the first clock count kept by the processing circuit and the second clock count updated.

6. The circuit device according to claim 4 , wherein
the processing circuit obtains the digital value based on the first clock count and the second clock count.

7. The circuit device according to claim 4 , wherein
the processing circuit includes a dither circuit configured to output a dither value, and adds the dither value to the first clock count to thereby update the first clock count.

8. The circuit device according to claim 4 , wherein
the signal generation circuit generates a third coarse-judging signal making a transition at a transition timing of the second clock signal anterior to the first coarse-judging signal, and a fourth coarse-judging signal making a transition at a transition timing of the second clock signal posterior to the second coarse-judging signal,
the phase comparison circuit performs a phase comparison between the second signal and the third coarse-judging signal to thereby output a fourth phase comparison signal, and performs a phase comparison between the second signal and the fourth coarse-judging signal to thereby output a fifth phase comparison signal, and
the processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the first phase comparison signal, the second phase comparison signal, the third phase comparison signal, the fourth phase comparison signal, and the fifth phase comparison signal, and converts the time difference between the first signal and the second signal into the digital value based on a result of the setting of the transition timing of the first signal and the transition timing of the fine-judging signal.

9. The circuit device according to claim 8 , wherein
the processing circuit variably controls a change step of the second clock count based on the second phase comparison signal, the third phase comparison signal, the fourth phase comparison signal, and the fifth phase comparison signal, and changes the second clock count as much as the change step to thereby update the second clock count.

10. The circuit device according to claim 1 , wherein
the clock generation circuit includes
an oscillation circuit configured to oscillate a resonator to thereby generate the second clock signal, and
a fractional NPLL circuit configured to generate the first clock signal based on the second clock signal.

11. The circuit device according to claim 1 , wherein
the clock generation circuit includes
a first oscillation circuit configured to oscillate a first resonator to thereby generate the first clock signal, and
a second oscillation circuit configured to oscillate a second resonator to thereby generate the second clock signal.

12. A physical quantity measurement device comprising:
the circuit device according to claim 10 ; and
the resonator.

13. A physical quantity measurement device comprising:
the circuit device according to

Assignees

• Seiko Epson Corp

Inventors

• Haneda Hideo

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03M1/201

  by dithering · CPC title