Digital linearization technique for charge pump based fractional phased-locked loop

Patent metadata

Field	Value
Publication number	US-9954542-B1
Application number	US-201715421884-A
Country	US
Kind code	B1
Filing date	Feb 1, 2017
Priority date	Feb 1, 2017
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

An apparatus includes an oscillator, a frequency divider, a phase circuit, a charge pump, and a filter. The frequency divider may generate an early feedback signal using a clock signal, and may assert a feedback signal a number of periods of the clock signal after asserting the early feedback signal. The phase circuit may generate a charge control signal using a reference clock signal and the feedback signal, and may generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal. The charge pump may charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal. The filter circuit may attenuate at least one frequency component of the frequency control signal. The oscillator circuit may modify a frequency of the clock signal using the frequency control signal.

First claim

What is claimed is:

1. An apparatus, comprising:
an oscillator circuit configured to generate a clock signal;
a frequency divider circuit configured to:
generate an early feedback signal using the clock signal; and
assert a feedback signal a number of periods of the clock signal after an assertion of the early feedback signal;

a phase circuit configured to:
generate a charge control signal using a reference clock signal and the feedback signal; and
generate a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal;

a charge pump circuit configured to selectively charge or discharge a circuit node using the charge control signal and the discharge control signal to generate a frequency control signal; and
a filter circuit configured to attenuate at least one frequency component included in the frequency control signal;
wherein the oscillator circuit is further configured to modify a frequency of the clock signal using the frequency control signal.

2. The apparatus of claim 1 , wherein the phase circuit is further configured to:
assert the charge control signal in response to an assertion of the reference clock signal; and
assert the discharge control signal in response to an assertion of the early feedback signal.

3. The apparatus of claim 2 , wherein the phase circuit is further configured to de-assert the charge control signal and the discharge control signal based at least on an assertion of the feedback signal.

4. The apparatus of claim 1 , wherein a frequency of the early feedback signal is based on a divisor value used by the frequency divider circuit, wherein the divisor value is an integer.

5. The apparatus of claim 4 , further including a modulation circuit configured to adjust the divisor value by an integer value.

6. The apparatus of claim 5 , wherein a frequency of the clock signal corresponds to a non-integer multiple of a frequency of the reference clock signal.

7. The apparatus of claim 1 , wherein the number of periods of the clock signal is programmable.

8. A method for operating a clock generation circuit, comprising:
generating, by an oscillator circuit, a clock signal;
generating, by a frequency divider circuit, an early feedback signal using the clock signal;
asserting, by the frequency divider circuit, a feedback signal a number of periods of the clock signal after asserting the early feedback signal;
generating, by a phase circuit, a charge control signal using a reference clock signal and the feedback signal;
generating, by the phase circuit, a discharge control signal using the early feedback signal, the reference clock signal, and the feedback signal; and
selectively charging and discharging, by a charge pump circuit, a circuit node to generate a frequency control signal based on the charge control signal and the discharge control signal;
attenuating, by a filter circuit, at least one frequency component included in the frequency control signal; and
modifying, by the oscillator circuit, a frequency of the clock signal using the frequency control signal.

9. The method of claim 8 , further comprising:
asserting the charge control signal in response to asserting the reference clock signal; and
asserting the discharge control signal in response to asserting the early feedback signal.

10. The method of claim 9 , further comprising de-asserting the charge control signal and the discharge control signal based at least on an assertion of the feedback signal.

11. The method of claim 8 , wherein generating the early feedback signal comprises using a divisor value to set a frequency of the early feedback signal, wherein the divisor value is an integer.

12. The method of claim 11 , further comprising adjusting, by a modulation circuit, the divisor value by an integer value.

13. The method of claim 12 , wherein the frequency of the clock signal is a non-integer multiple of a frequency of the reference clock signal.

14. The method of claim 8 , further comprising adjusting the number of periods of the clock signal.

15. A system, comprising:
a clock source configured to generate a reference clock signal;
a processor configured to select a multiplication value for determining a frequency of a clock signal based on a frequency of the reference clock signal;
a clock generation circuit configured to:
generate the clock signal;
generate an early feedback signal based on the clock signal and the multiplication value;
assert a feedback signal a number of periods of the clock signal after the early feedback signal is asserted;
generate a charge control signal based on the reference clock signal and the feedback signal;
generate a discharge control signal based on the early feedback signal, the reference clock signal, and the feedback signal;
selectively charge and discharge the a circuit node to generate a frequency control signal based on the charge control signal and discharge control signal;
attenuate at least one frequency component included in the frequency control signal; and
modify a frequency of the clock signal using the frequency control signal.

16. The system of claim 15 , wherein the clock generation circuit is further configured to:
assert the charge control signal in response to an assertion of the reference clock signal; and
assert the discharge control signal in response to an assertion of the early feedback signal.

17. The system of claim 16 , wherein the clock generation circuit is further configured to de-assert the charge control signal and the discharge control signal based at least on an assertion of the feedback signal.

18. The system of claim 15 , wherein a frequency of the feedback signal and a frequency of the early feedback signal are based on a divisor value used by the clock generation circuit, wherein the divisor value is an integer based on the multiplication value.

19. The system of claim 18 , wherein the clock generation circuit is further configured to adjust the divisor value by an integer value.

20. The system of claim 15 , wherein a frequency of the clock signal corresponds to a non-integer multiple of a frequency of the reference clock signal, and wherein the non-integer multiple corresponds to the multiplication value.

Assignees

• Apple Inc

Inventors

• Kong Robert K
• Zhao Feng
• Deng Wei

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/1974 Primary

  for fractional frequency division · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/191

  using at least two different signals from the frequency divider or the counter for determining the time difference (H03L7/193, H03L7/195 take precedence) · CPC title