Active device circuit substrate

Patent metadata

Field	Value
Publication number	US-2016126356-A1
Application number	US-201514819434-A
Country	US
Kind code	A1
Filing date	Aug 6, 2015
Priority date	Oct 30, 2014
Publication date	May 5, 2016
Grant date	—

Abstract

An active device circuit substrate includes a substrate, a plurality of active devices, and a first planarization layer. Each active device includes a gate electrode, a channel layer stacked with the gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are disposed on the channel layer and located on opposite sides of the channel layer to define a channel area of the channel layer. The active devices include a first active device and a second active device. The first active device is disposed between the first planarization layer and the substrate, and the first planarization layer is disposed between the first active device and the second active device. A minimum linear distance between the channel area of the first active device and the channel area of the second active device along a direction parallel to the substrate is not smaller than 5 μm.

First claim

What is claimed is:

1 . An active device circuit substrate, comprising:
a substrate; a plurality of active devices, disposed on the substrate, each of the active devices comprising a gate electrode, a channel layer, a source electrode, and a drain electrode, wherein the channel layer is stacked with the gate electrode, and the source electrode and the drain electrode are disposed on the channel layer and located on opposite sides of the channel layer, so as to define a channel area of the channel layer; and a first planarization layer, disposed on the substrate, wherein the active devices comprise at least one first active device and at least one second active device, the at least one first active device is disposed between the first planarization layer and the substrate, and the first planarization layer is disposed between the at least one first active device and the at least one second active device, and a minimum linear distance between the channel area of the first active device and the channel area of the second active device along a direction parallel to the substrate is larger than or equal to 5 μm.

2 . The active device circuit substrate of claim 1 , wherein the channel layer of each of the active devices is an oxide semiconductor layer.

3 . The active device circuit substrate of claim 1 , wherein the first planarization layer is an organic material layer, a silicon-based material layer, a mixed layer of an organic material and a silicon-based material, or a stacked layer of at least two of the above layers.

4 . The active device circuit substrate of claim 1 , wherein a thickness of the first planarization layer is 0.5 μm to 5 μm.

5 . The active device circuit substrate of claim 1 , wherein the first planarization layer comprises at least one through hole, and the at least one second active device is electrically connected to the at least one first active device via the at least one through hole.

6 . The active device circuit substrate of claim 1 , wherein the at least one second active device is electrically insulated from the at least one first active device via the first planarization layer.

7 . The active device circuit substrate of claim 1 , further comprising:
a first protective layer, wherein the at least one second active device is disposed between the first protective layer and the first planarization layer.

8 . The active device circuit substrate of claim 7 , wherein the first protective layer is an inorganic material layer.

9 . The active device circuit substrate of claim 7 , further comprising:
a second planarization layer, wherein the first protective layer is disposed between the at least one second active device and the second planarization layer.

10 . The active device circuit substrate of claim 1 , further comprising:
a second protective layer, disposed between the first planarization layer and the at least one first active device.

11 . The active device circuit substrate of claim 1 , wherein the source electrode and the drain electrode of the first active device are arranged in a direction perpendicular to a direction that the first active device is arranged, and the source electrode and the drain electrode of the second active device are arranged in a direction perpendicular to a direction that the second active device is arranged.

12 . The active device circuit substrate of claim 1 , wherein the source electrode and the drain electrode of the first active device are arranged in a direction parallel to a direction that the first active device is arranged, and the source electrode and the drain electrode of the second active device are arranged in a direction parallel to a direction that the second active device is arranged.

13 . The active device circuit substrate of claim 1 , wherein the source electrode and the drain electrode of the first active device are arranged in a direction that is neither parallel nor perpendicular to a direction that the first active device is arranged, and the source electrode and the drain electrode of the second active device are arranged in a direction that is neither parallel nor perpendicular to a direction that the second active device is arranged.

Assignees

• E Ink Holdings Inc

Inventors

• Hsu Cheng-Hang
• Yu Tzung-Wei
• Hsu Yu-Lin
• Shinn Ted-Hong

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title