Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

Patent metadata

Field	Value
Publication number	US-11201138-B2
Application number	US-201916717068-A
Country	US
Kind code	B2
Filing date	Dec 17, 2019
Priority date	Sep 22, 2016
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A method of manufacturing a multi-layer wafer is provided. Under bump metallization (UMB) pads are created on each of two heterogeneous wafers. A conductive means is applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The stress compensating polymer layer has a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition.

First claim

What is claimed is:

1. A method of manufacturing a multi-layer wafer comprising:
creating under bump metallization pads on each of two heterogeneous wafers;
applying a conductive means above the under bump metallization pads on at least one of the two heterogeneous wafers;
applying at least one stress compensating polymer layer to at least one of the two heterogeneous wafers, the at least one stress compensating polymer layer having a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition; and low temperature bonding the two heterogeneous wafers to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.

2. The method of claim 1 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si, CMOS and glass, CMOS and sapphire, CMOS and SiC on Si, CMOS and diamond on Si, or CMOS and sapphire on Si.

3. The method of claim 1 , wherein the at least one stress compensating polymer layer is formed on the at least one of the two heterogeneous wafer by: applying a liquid polymer to the at least one of the two heterogeneous wafers; and spinning the at least one of the two heterogeneous wafers to evenly distribute the liquid polymer.

4. The method of claim 1 , wherein the conductive means is one of solder balls, conductive paste, or solder topped copper pillars.

5. The method of claim 1 , wherein the conductive means is formed from one of In, InSn, InBi, Sn alloys, other high Sn solder alloys, Pb, PbSn, other high lead alloys, Cu, Ni, Au, Ag, Pt, Pd, or combinations therein that can be contacted, joined and bonded at low temperature or room temperature.

6. The method of claim 1 , further comprising:
applying a resist layer to at least one of the two heterogeneous wafers; and
etching the resist layer to define holes in the resist layer above the under bump metallization pads such that the conductive means fills in the holes upon application.

7. The method of claim 6 , further comprising the resist layers the resist layer applied to at least one of the two heterogeneous wafers.

8. The method of claim 1 , wherein each under bump metallization pad has a complementary under bump metallization pad located at a mirrored position on the opposite heterogeneous wafer such that the complementary under bump metallization pads align when the heterogeneous wafers are bonded together.

9. The method of claim 1 , further comprising creating channels between die on at least one of the two heterogeneous wafers.

10. The method of claim 9 , wherein the channels are back filled with one of oxide or polymer to create a channel oxide deposition.

11. The method of claim 1 , further comprising creating islands of material in at least one heterogeneous wafer by at least one of depositing or growing the material.

12. The method of claim 1 , further comprising thinning at least one of the heterogeneous wafers of the multi-layer wafer pair.

13. The method of claim 12 , further comprising forming interconnection vias between the two heterogeneous wafers of the multi-layer wafer pair.

14. The method of claim 1 , wherein the two heterogeneous wafers are low temperature bonded at a temperature range of room temperature to 100° C.

Assignees

• IBM

Inventors

• Dang Bing
• Hung Li-Wen
• Knickerbocker John U
• Nah Jae-Woong

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title