High bandwidth module

Patent metadata

Field	Value
Publication number	US-11201136-B2
Application number	US-202016814139-A
Country	US
Kind code	B2
Filing date	Mar 10, 2020
Priority date	Mar 10, 2020
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

First claim

What is claimed is:

1. A module comprising:
a substrate having a plurality of contact regions; and
a spacer-chip assembly, in turn comprising:
at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads;
a spacer wafer, said at least first and second semiconductor dies being secured to said spacer wafer, said spacer wafer including at least first and second semiconductor circuit features coupled to a first portion of said contact pads of said at least first and second semiconductor dies, said spacer wafer including wiring electrically coupling said at least first and second semiconductor dies via a second portion of said contact pads; said spacer wafer having a plurality of holes formed therethrough, said plurality of electrical interconnect pillars extending through said holes and being secured to said contact regions on said substrate.

2. The module of claim 1 , wherein said semiconductor circuit features comprise decoupling capacitors.

3. The module of claim 2 , further comprising underfill disposed in said holes.

4. The module of claim 3 , further comprising over-mold between said at least first and second semiconductor dies.

5. The module of claim 4 , wherein said holes are sized to receive a single one of said pillars.

6. The module of claim 4 , wherein said holes are sized to receive multiple ones of said pillars.

7. The module of claim 6 , wherein said pillars comprise under bump metallurgy (UBM).

8. The module of claim 4 , further comprising a glass-filled pocket formed in said spacer wafer, wherein:
at least a portion of said holes are formed in said glass;
said first semiconductor die comprises a silicon chip;
said second semiconductor die comprises a silicon carbide chip; and
those of said interconnect pillars associated with said silicon carbide chip extend into those of said holes in said glass.

9. The module of claim 4 , wherein said plurality of electrical interconnect pillars are secured to contact regions on said substrate via dippable paste.

10. The module of claim 9 , wherein said pillars comprise copper and said dippable paste comprises copper.

11. The module of claim 9 , wherein said pillars comprise copper and said dippable paste comprises lead-free solder.

12. The module of claim 4 , wherein said plurality of electrical interconnect pillars are secured to contact regions on said substrate via controlled collapse chip connection (C4).

13. The module of claim 4 , wherein said spacer wafer comprises glass and said decoupling capacitors comprise thin film capacitors.

14. The module of claim 4 , wherein said spacer wafer comprises silicon and said decoupling capacitors are selected from the group consisting of deep trench capacitors and MIM (Metal-Insulator-Metal) capacitors.

Assignees

• IBM

Inventors

• Arvin Charles Leon
• Singh Bhupender
• Li Shidong
• Muzzy Chris
• Wassick Thomas Anthony

Classifications

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title