Display having an amorphous silicon light shield below a thin film transistor

Patent metadata

Field	Value
Publication number	US-11201120-B2
Application number	US-201716070271-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Apr 28, 2017
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

In embodiments of the present disclosure, there is provided a display substrate assembly including: a base substrate; a light shielding layer on the base substrate; and an active layer of a thin film transistor, above the base substrate. An orthographic projection of the active layer on the base substrate in a thickness direction of the base substrate is within an orthographic projection of the light shielding layer on the base substrate in the thickness direction of the base substrate, and the light shielding layer includes an ion-doped amorphous silicon layer. In embodiments of the present disclosure, there is also provided a method of manufacturing a display substrate assembly and a display apparatus including the display substrate assembly.

First claim

What is claimed is:

1. A display substrate assembly, comprising:
a base substrate;
a light shielding layer on the base substrate; and
an active layer of a thin film transistor, above the base substrate;
wherein an orthographic projection of the active layer on the base substrate in a thickness direction of the base substrate is within an orthographic projection of the light shielding layer on the base substrate in the thickness direction of the base substrate, and the light shielding layer comprises an amorphous silicon layer doped with boron ions or phosphorus ions with a doping concentration of 5×10 14 to 9×10 14 cm −2 .

2. The display substrate assembly of claim 1 , further comprising:
a buffer layer on the base substrate;
a first insulating layer on the buffer layer; and
a second insulating layer on the light shielding layer;
wherein, the light shielding layer is between the first insulating layer and the second insulating layer, and the second insulating layer is between the light shielding layer and the active layer.

3. The display substrate assembly of claim 2 , wherein orthogonal projections of the active layer, the first insulating layer, the light shielding layer and the second insulating layer on the base substrate in the thickness direction of the base substrate are completely overlapped.

4. The display substrate assembly of claim 2 , wherein the buffer layer, the first insulating layer, the light shielding layer, the second insulating layer and the active layer are stacked on the base substrate in that order from the bottom to the top.

5. The display substrate assembly of claim 2 , wherein the buffer layer comprises silicon nitride material.

6. The display substrate assembly of claim 2 , wherein the buffer layer has a thickness of 200 Å to 1000 Å.

7. The display substrate assembly of claim 2 , wherein the first insulating layer and the second insulating layer comprise silicon oxide material.

8. The display substrate assembly of claim 2 , wherein the first insulating layer has a thickness of 500 Å to 3000 Å, and the second insulating layer has a thickness of 1000 Å to 4000 Å.

9. The display substrate assembly of claim 1 , wherein the light shielding layer has a thickness of 500 Å to 1600 Å.

10. The display substrate assembly of claim 1 , wherein the active layer comprises polysilicon material.

11. A display apparatus comprising the display substrate assembly of claim 1 .

12. A method of manufacturing a display substrate assembly, the method comprising:
providing a base substrate; and
forming an active layer of a thin film transistor and a light shielding layer above the base substrate so that an orthographic projection of the active layer on the base substrate in a thickness direction of the base substrate is within an orthogonal projection of the light shielding layer on the base substrate in the thickness direction of the base substrate, and the light shielding layer is formed of an ion-doped amorphous silicon layer,
wherein the light shielding layer comprises an amorphous silicon layer doped with boron ions or phosphorus ions with a doping concentration of 5×10 14 to 9×10 14 cm −2 .

13. The method of claim 12 , further comprising:
forming a buffer layer, a layer of first insulating material, a layer of second insulating material and a layer of semiconductor material, on the base substrate; and
patterning, with one mask, the layer of first insulating material, the ion-doped amorphous silicon layer, the layer of second insulating material and the layer of semiconductor material, to form a first insulating layer, the light shielding layer, a second insulating layer and the active layer, respectively.

14. The method of claim 13 , wherein the step of forming a buffer layer, a layer of first insulating material, the light shielding layer, a layer of second insulating material and a layer of semiconductor material, on the base substrate, comprises:
forming the buffer layer on the base substrate;
forming the layer of first insulating material on the buffer layer;
forming a first amorphous silicon layer on the layer of first insulating material;
forming the layer of second insulating material on the first amorphous silicon layer;
forming a second amorphous silicon layer on the layer of second insulating material;
implementing an ion doping on the first amorphous silicon layer, and annealing the first ion-doped amorphous silicon layer, to form the light shielding layer; and
annealing the second amorphous silicon layer to convert the second amorphous silicon layer into a polysilicon layer as the layer of semiconductor material.

15. The method of claim 14 , wherein the step of patterning, with one mask, the layer of first insulating material, the ion-doped amorphous silicon layer, the layer of second insulating material and the layer of semiconductor material, comprises:
forming a pattern of photoresist on the layer of semiconductor material with the one mask;
etching, by using the pattern of photoresist as a mask in an etching process, the layer of first insulating material, the ion-doped amorphous silicon layer, the layer of second insulating material, and the layer of semiconductor material, to form the first insulating layer, the light shielding layer, the second insulating layer, and the active layer, respectively; and
stripping off the photoresist.

16. The method of claim 15 , wherein, when the layer of first insulating material and the layer of second insulating material are etched, etch rates of the layer of first insulating material and the layer of second insulating material are approximately the same.

17. The method of claim 14 , wherein, the step of implementing an ion doping on the first amorphous silicon layer, comprises:
implanting, by adopting ion implantation process parameters including a voltage of 30 KV and an ion implantation dose of 5E14 to 9E14, boron ions or phosphorus ions into the first amorphous silicon layer.

18. The method of claim 14 , wherein, the layer of first insulating material and the layer of second insulating material are formed of silicon oxide.

19. The method of claim 13 , wherein, the buffer layer is formed of silicon nitride.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Yao Qi
• Cao Zhanfeng
• Zhang Feng
• Wang Jiushi

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W42/20 Primary

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title