LTPS TFT Having Dual Gate Structure and Method for Forming LTPS TFT

Patent metadata

Field	Value
Publication number	US-2016133473-A1
Application number	US-201414415607-A
Country	US
Kind code	A1
Filing date	Nov 14, 2014
Priority date	Nov 11, 2014
Publication date	May 12, 2016
Grant date	—

Abstract

The present invention proposes a low temperature poly-silicon thin-film transistor having a dual-gate structure and a method for forming the low temperature poly-silicon thin-film transistor. The low temperature poly-silicon thin-film transistor includes: a substrate, one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate, an NMOS disposed on the barrier layer, and a PMOS disposed on the barrier layer. The NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure. The present invention proposes a low temperature poly-silicon thin-film transistor with a more stabilized I-V characteristic, better driving ability, low power consumption, and higher production yield.

First claim

What is claimed is:

1 . A low temperature poly-silicon thin-film transistor (LIPS TFT) having a dual-gate structure, comprising:
a substrate; one or more patterned amorphous silicon (a-Si) layers, disposed in a barrier layer on the substrate, for forming a bottom gate; an N-type metal-oxide-semiconductor (NMOS) disposed on the barrier layer; and a P-type metal-oxide semiconductor (PMOS) disposed on the barrier layer; wherein the NMOS comprises a patterned gate electrode (GE) layer as a top gate, and the patterned GE layer and the bottom gate formed by the one or more patterned a-Si layers form a dual-gate structure.

2 . The LTPS TFT as claimed in claim 1 , wherein the NMOS comprises:
a first patterned poly-silicon (poly-si) layer; two N − -type layers, comprising an inner side connected to two outer sides of the first patterned poly-Si layer, respectively; two N + -type layers, connected to two outer sides of the two N − -type layers, respectively; and a gate insulation layer, disposed on the first patterned poly-Si layer, the two N − -type layers, the two N + -type layers, and the barrier layer.

3 . The LIPS TFT as claimed in claim 2 , wherein the PMOS comprises:
a second patterned poly-Si layer; two P + -type layers, connected to two outer sides of the second patterned poly-Si layer, respectively; and the gate insulation layer, disposed on the second patterned poly-Si layer and the two P + -type layers.

4 . The LIPS TFT as claimed in claim 3 , wherein the gate insulation layer insulates and separates the patterned GE layer of the NMOS from the first patterned poly-Si layer for forming an N-type channel on the first patterned poly-Si layer.

5 . The LTPS TFT as claimed in claim 4 , wherein the PMOS comprises a patterned GE layer, and the gate insulation layer insulates and separates the patterned GE layer of the PMOS from the second patterned poly-Si layer so that the second patterned poly-Si layer forms a P-type channel.

6 . The LTPS TFT as claimed in claim 5 further comprising:
an inter-level dielectric (ILD), formed on the patterned GE layer and the gate insulation layer;
a plurality of via holes, penetrating the ILD and the gate insulation layer.

7 . The LTPS TFT as claimed in claim 6 , further comprising:
a plurality of patterned source/drain electrodes, connected to the P + -type layer of the PMOS and the N + -type layer of the NMOS through the plurality of via holes, respectively.

8 . The LTPS TFT as claimed in claim 7 , wherein the patterned GE layer is made of a first metal and comprises a vertical extension connected to the N + -type layer connected to the first patterned a-Si layer through the N-type channel to form the LTPS TFT having the dual-gate structure.

9 . A method for forming an LTPS TFT having a dual-gate structure, comprising:
forming a plurality of patterned a-Si layers disposed on a substrate; forming a barrier layer on the plurality of patterned a-Si layers; forming a first patterned poly-Si layer and a second patterned poly-Si layer on the barrier layer; coating a first photoresist layer on a top surface of the second patterned poly-Si layer and on a lateral side of the second patterned poly-Si layer; forming an N-type channel by doping the first patterned poly-Si layer; removing the first photoresist layer from the second patterned poly-Si layer; forming a gate insulation layer on both of the second patterned poly-Si layer and the first patterned poly-Si layer where the N-type channel is formed; forming a second photoresist layer on the gate insulation layer, and doping the second patterned poly-Si layer to form a P + -type layer; removing the second photoresist layer from the gate insulation layer, and coating a third photoresist layer on the gate insulation layer; removing a part of the third photoresist layer, a part of the gate insulation layer, and a part of the barrier layer by performing exposing and developing processes, for forming a plurality of openings; N + doping a part of the patterned a-Si layer and a part of the first patterned poly-Si layer which are not covered by the gate insulation layer; forming a plurality of patterned GE layers on the gate insulation layer; N − doping the first patterned poly-Si layer and the second patterned poly-Si layer with the plurality of patterned GE layers as a second shielding layer, the plurality of patterned GE layers corresponding to the first patterned poly-Si layer connected to and conducted to the N + -type layer of the patterned a-Si layer, and the plurality of patterned GE layers and the N + -type layer forming a dual-gate structure; forming an ILD on the plurality of patterned GE layers and the gate insulation layer; forming a plurality of via holes penetrating the ILD and the gate insulation layer; and forming a plurality of patterned source/drain electrodes through the plurality of via holes, the plurality of patterned source/drain electrodes connected to the P + -type layer which is connected to the second patterned poly-Si layer to form a PMOS, and the plurality of patterned source/drain electrodes connected to the N + -type layer which is connected to the first patterned poly-Si layer to form an NMOS.

10 . The method as claimed in claim 9 , wherein the N + -type layer is doped with the exposed part of the patterned a-Si layer for forming an ohmic contact with a metallic electrode.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Wang Xiaoxiao
• Hsiao Hsiang Chih
• Du Peng
• Su Chang-I
• Xu Hongyuan
• Sun Bo

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10D64/01324 Primary

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D86/0231 Primary

  using masks, e.g. half-tone masks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title