Counter readout circuit

Patent metadata

Field	Value
Publication number	US-11200480-B2
Application number	US-201916690772-A
Country	US
Kind code	B2
Filing date	Nov 21, 2019
Priority date	Nov 26, 2018
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.

First claim

What is claimed is:

1. A counter readout circuit comprising:
a plurality of counter registers that each comprise a counter configured to count cycles of a clock signal; and
an output data computing circuit configured to calculate a calculated data value by adding a counter value of a selected one of the plurality of counter registers to a total clock count, and configured to output the calculated data, wherein:
the total clock count is a number of clock cycles between a first timing and a second timing,
the first timing is a time at which the counter readout circuit receives a first data readout request common to all of the counter registers, and
the second timing is a time at which the counter readout circuit receives a second data readout request specific to the selected one of the counter registers.

2. The counter readout circuit according to claim 1 , further comprising:
a counter data computing circuit configured to calculate the total clock count,
wherein each of the plurality of counter registers further comprises a count zero enable circuit configured to, when the counter value reaches zero, set a flag indicating that the counter value of the respective counter register has reached the specified value, and
wherein, when the flag is set, the counter is configured to stop counting and set the counter value to the total clock count.

3. The counter readout circuit according to claim 2 , wherein the output data computing circuit further comprises a selector that is configured to:
when the flag of the counter of the selected one of the counter registers is not set, output the calculated data value calculated by the output data computing circuit, and
when the flag of the selected counter is set, output the counter value set in the counter.

4. The counter readout circuit according to claim 3 , further comprising:
an L-ary counter, wherein L is a predetermined number,
wherein the output data computing circuit and the counter data computing circuit are each configured to calculate the total clock count by adding a value of a low order digit of the L-ary counter to a product of a value of a high-order digit of the L-ary counter and the predetermined number.

5. The counter readout circuit according to claim 2 , further comprising:
an L-ary counter, wherein L is a predetermined number,
wherein the output data computing circuit and the counter data computing circuit are each configured to calculate the total clock count by adding a value of a low order digit of the L-ary counter to a product of a value of a high-order digit of the L-ary counter and the predetermined number.

Assignees

• Murata Manufacturing Co

Inventors

• Matsuyama Satoru
• Matsumura Satoshi
• Nakamuta Kazuhiro

Classifications

• H03D13/001

  in which a pulse counter is used followed by a conversion into an analog signal · CPC title

• G06M1/27 Primary

  for representing the result of count in the form of electric signals, e.g. by sensing markings on the counter drum · CPC title

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C7/1066 Primary

  Output synchronization · CPC title