Bounded latency and command non service methods and apparatus

US11200003B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11200003-B2
Application numberUS-202016925185-A
CountryUS
Kind codeB2
Filing dateJul 9, 2020
Priority dateOct 24, 2018
Publication dateDec 14, 2021
Grant dateDec 14, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.

First claim

Opening claim text (preview).

What is claimed is: 1. A solid state drive, comprising: a controller configured to: receive one or more commands at a flash translation layer; timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded; add each command received at the flash translation layer to a queue; determine, for a next command to be performed in the queue, whether the respective command has timed out before being transferred from the queue for being performed based on the timestamp of the respective command; and send, for a command that has been determined to be timed out, a message to a host that the respective command has timed out. 2. The solid state drive of claim 1 , wherein receiving the one or more commands at the flash translation layer includes receiving multiple commands at the flash translation layer. 3. The solid state drive of claim 1 , wherein the flash translation layer is disposed in a memory device, and the memory device performs the receiving the one or more commands, the timestamping each command, the adding the command to the queue, the determining whether a command has timed out, and the sending the message to the host. 4. The solid state drive of claim 1 , wherein the controller is further configured to: remove from the queue each command that has been determined to be timed out. 5. The solid state drive of claim 1 , further comprising: an interface, wherein the interface is configured to: timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded; manage one or more data requests from flash memory; determine instances of when a timed out condition is present; and limit the flash translation layer from sending timed out conditions for activities that have already been notified as timed out. 6. The solid state drive of claim 1 , further comprising: one or more flash memories coupled to the controller, wherein the one or more flash memories store data associated with the one or more commands. 7. The solid state drive of claim 6 , wherein the one or more flash memories comprises one or more dies. 8. A solid state drive, comprising: a controller is configured to: receive one or more commands at a flash translation layer, wherein each command is required to be performed at a specified die; timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded; add each command received at the flash translation layer to a queue; determine, for a next command to be performed in the queue, whether the respective command has timed out before being transferred to the specified die based on the timestamp of the respective command; send, for a command that has been determined to be timed out, a message to a host that the respective command has timed out; determine, for a next command to be performed in the queue that has not timed out, whether the respective command is expected to time out based on a latency for completion and the timestamp of the respective command, the latency for completion being based on a number of commands to be processed (i) before the respective command and (ii) by the specified die that is to perform the respective command; and notify, for a next command that is determined to be expected to time out, the host that the respective command is expected to time out. 9. The solid state drive of claim 8 , wherein receiving the one or more commands at the flash translation layer includes receiving multiple commands at the flash translation layer. 10. The solid state drive of claim 8 , wherein the controller is further configured to: remove from the queue each command that has been determined to be timed out. 11. The solid state drive of claim 8 , wherein the controller is further configured to: determine, for each command in the queue, whether the respective command has timed out before being transferred to the specified die based on the timestamp of the respective command; and determine, for each command in the queue that has not timed out, whether the respective command is expected to time out based on the respective latency for completion and the timestamp of the respective command. 12. The solid state drive of claim 8 , further comprising: an interface, wherein the interface is configured to: timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded; manage one or more data requests from flash memory; determine instances of when a timed out condition is present; and limit the flash translation layer from sending timed out conditions for activities that have already been notified as timed out. 13. The solid state drive of claim 8 , further comprising: one or more flash memories coupled to the controller, wherein the one or more flash memories store data associated with the one or more commands. 14. The solid state drive of claim 13 , wherein the one or more flash memories comprises one or more dies. 15. A solid state drive, comprising: a controller is configured to: receive one or more commands at a flash translation layer, wherein each command is required to be performed at a specified die; timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded; add each command received at the flash translation layer to a queue; determine, for a next command to be performed in the queue that has not timed out, whether the respective command is expected to time out based on a latency for completion and the timestamp of the respective command, the latency for completion being based on a number of commands to be processed (i) before the respective command and (ii) by the specified die that is to perform the respective command; and notify, for a next command that is determined to be expected to time out, a host that the respective command is expected to time out. 16. The solid state drive of claim 15 , wherein receiving the one or more commands at the flash translation layer includes receiving multiple commands at the flash translation layer, wherein the multiple commands are to be performed by a memory arrangement. 17. The solid state drive of claim 15 , wherein the controller is further configured to: remove from the queue each command that has been determined to be timed out. 18. The solid state drive of claim 15 , further comprising: an interface, wherein the interface is configured to: timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded; manage one or more data requests from flash memory; determine instances of when a timed out condition is present; and limit the flash translation layer from sending timed out conditions for activities that have already been notified as timed out. 19. The solid state drive of claim 15 , further comprising: one or more flash memories coupled to the controller, wherein the one or more flash memories store data associated with the one or more commands. 20. The soli

Assignees

Inventors

Classifications

  • Timestamp · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

  • with latency improvement · CPC title

  • G06F3/0659Primary

    Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

  • Threshold · CPC title

Patent family

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Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11200003B2 cover?
The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.
Who is the assignee on this patent?
Western Digital Tech Inc
What technology area does this patent fall under?
Primary CPC classification G06F3/0659. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 14 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).