Apparatus for obsolete mapping counting in NAND-based storage devices

Patent metadata

Field	Value
Publication number	US-11199983-B2
Application number	US-201916538619-A
Country	US
Kind code	B2
Filing date	Aug 12, 2019
Priority date	Aug 12, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

In one or more embodiments, a NAND-based data storage device includes a device controller configured to receive a memory write command from a host specifying a set of memory locations to be written to, and to determine whether the command is for a random write. In response to the determination, the device controller is further configured to configure one or more update entries to an update layer of a mapping architecture of the device for the set of memory locations, such that the one or more update entries are respectively aligned with a size of a pre-defined MRU of mapping data for the device. By aligning the update entries with the smaller MRU, smaller regions of memory may be flagged as obsolete, increasing efficiency. In one embodiment, the device controller further includes a RAM, and the update layer is stored in the RAM.

First claim

What is claimed is:

1. A NAND-based data storage device, comprising:
a device controller configured to:
receive a memory write command from a host specifying a set of memory locations to be written to;
determine that the memory write command is for a random write or a sequential write, wherein the sequential write is part of a master layer (mLayer) that is not to be loaded to random access memory (RAM) in entirety;
determine that one or more update entries for an update layer (uLayer) of a mapping architecture of the device for the set of memory locations fails to align with a size of a pre-defined minimum reading unit (MRU) of mapping architecture data for the device, wherein the mLayer is separate from the uLayer; and
in response to the determination that one or more update entries for the uLayer of a mapping architecture of the device for the set of memory locations fails to align, configure the one or more update entries for the uLayer of the mapping architecture of the device for the set of memory locations, such that the one or more update entries are respectively aligned with a size of the MRU of mapping architecture data for the device, wherein the configuring comprises modifying the one or more update entries such that the modified one or more update entries are aligned with the size of the pre-defined MRU.

2. The data storage device of claim 1 , wherein the device controller further comprises the random access memory (RAM), and wherein the uLayer is stored in the RAM.

3. The data storage device of claim 1 , wherein the mapping architecture of the device is a logical to physical (L2P) mapping architecture further comprising a mLayer, the mLayer comprising a set of master layer units (mSet), each mSet including a mapping for a pre-defined number of memory locations of the device, and wherein the size of the MRU is less than a pre-defined size of the mSet.

4. The data storage device of claim 3 wherein the size of the MRU is equal to the size of a logical page defined for the NAND-based storage device.

5. The data storage device of claim 3 , wherein the device controller is further configured to read a portion of the mSet equal in size to any multiple of the size of the MRU.

6. The data storage device of claim 3 , wherein a ratio of the size of the MRU to the pre-defined size of the mSet is a regular fraction whose numerator and denominator are both powers of 2.

7. The data storage device of claim 1 , wherein the mapping architecture is a logical to physical (L2P) mapping architecture, and wherein a mLayer of the L2P mapping architecture is stored in the NAND-based storage, the mLayer comprising a set of master layer units (mSet), each mSet including a mapping for a pre-defined number of memory locations of the device.

8. The data storage device of claim 7 , wherein the device controller further comprises the RAM, the RAM storing a cached address table (CAT) into which the MRU is read from the mLayer.

9. The data storage device of claim 7 , wherein the device controller is further configured to:
determine whether a fraction of the mSet may be read by the device, and in response to the determination, configure one or more update entries for the uLayer of the mapping architecture of the device for the set of memory locations, such that the one or more update entries are respectively aligned with the size of the MRU of the mapping architecture for the device.

10. The data storage device of claim 1 , wherein the update layer entries each include an data obsolete flag, and wherein the device controller is further configured to determine whether all previous mappings for the memory location described by an update layer entry are resolved as obsolete, and, in response to the determination, set the data obsolete flag.

11. A non-volatile storage device, comprising:
a NAND-based storage, in which is stored a master layer of a logical to physical (L2P) mapping architecture; and
a device controller including a random access memory (RAM), wherein an update layer of the L2P mapping architecture is stored in the RAM;
wherein, in response to a write command received from a host, the device controller is configured to:
determine that the write command is for a random write or a sequential write, wherein the sequential write is part of a master layer (mLayer) that is not to be loaded to random access memory (RAM) in entirety;
translate logical addresses of the write command to physical addresses in the NAND-based storage;
generate one or more entries to the update layer (uLayer) indicating a mapping of the logical addresses to the physical addresses; determine that the one or more entries for the uLayer fails to align with a size of a pre-defined minimum reading unit (MRU) of mapping architecture data for the device, wherein the mLayer is separate from the uLayer; and
align the one or more entries with a size of the MRU of the device, wherein the aligning comprises modifying the one or more update entries such that the modified one or more update entries are aligned with the size of the pre-defined MRU.

12. The non-volatile storage device of claim 11 , wherein the mLayer of the L2P mapping architecture includes master layer units (mSet) of a pre-defined size, and wherein the size of the MRU of the device is less than the size of the mSet.

13. The non-volatile storage device of claim 11 , wherein the MRU of the device refers to a number of memory locations equal to those included in a logical page defined for the NAND-based storage.

14. The non-volatile storage device of claim 11 , wherein the master layer of the L2P mapping architecture includes a set of mSet, each mSet having a pre-defined size.

15. The non-volatile storage device of claim 14 , wherein a ratio of the pre-defined size of the MRU to the pre-defined size of the mSet is a regular fraction whose numerator and denominator are both powers of 2.

16. The non-volatile storage device of claim 11 , wherein the device controller is further configured to, prior to generating the one or more entries, determine if the write command is for a random write.

17. The non-volatile storage device of claim 11 , wherein the device controller is further configured to save the one or more generated entries to the uLayer in the RAM.

18. An apparatus, comprising:
means for receiving a write command from a host;
means for determining if the write command is a random write or a sequential write, wherein the sequential write is part of a master layer (mLayer) that is not to be loaded to random access memory (RAM) in entirety;
means for translating logical addresses of the write command to physical addresses of NAND-based storage means coupled to the apparatus;
means for generating one or more entries to an update layer (uLayer) of a logical to physical (L2P) mapping architecture for the NAND-based storage means, the one or more entries indicating a mapping of the logical addresses to the physical addresses; means for determining that the one or more entries for the uLayer fails to align with a size of a pre-defined minimum reading unit (MRU) of mapping architecture data for the apparatus, wherein the mLayer is separate from the uLayer; and
means for aligning the one or more entries with a size of the MRU of the apparatus, wherein the aligning comprises modifying the one or more update entries such that the modified one or more update entries are aligned with the size of the pre-defined MRU.

19. The apparatus of claim 18 , further comprising the NAND-based storage means, wherein a mLayer of the L2P m

Assignees

• Western Digital Tech Inc

Inventors

• Frid Marina
• Genshaft Igor

Classifications

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F12/04

  Addressing variable-length words or parts of words · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title