Method of forming a low loss electronics assembly

Patent metadata

Field	Value
Publication number	US-11197376-B2
Application number	US-201916598595-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Oct 10, 2019
Publication date	Dec 7, 2021
Grant date	Dec 7, 2021

Abstract

A method of forming an electronics assembly includes providing a substrate, attaching an electronics component to the substrate, disposing one or more dielectric ramps on the substrate along at least a portion of a perimeter of the electronics component, disposing a first ground plane over the substrate and the dielectric ramp(s), disposing a first dielectric over the first ground plane, disposing a stripline over the first dielectric, disposing a second dielectric over the stripline and the first dielectric, and disposing a second ground plane over the second dielectric.

First claim

What is claimed is:

1. A method of forming an electronics assembly, the method comprising:
providing a substrate;
attaching an electronics component to the substrate;
disposing one or more dielectric ramps on the substrate along at least a portion of a perimeter of the electronics component;
disposing a first ground plane over the substrate and the one or more dielectric ramps;
disposing a first dielectric over the first ground plane;
disposing a stripline over the first dielectric;
disposing a second dielectric over the stripline and the first dielectric; and
disposing a second ground plane over the second dielectric.

2. The method of claim 1 , wherein said disposing the one or more dielectric ramps comprises printing the one or more dielectric ramps, wherein said disposing the first ground plane comprises printing the first ground plane, wherein said disposing the first dielectric comprises printing the first dielectric, wherein said disposing the stripline comprises printing the stripline, wherein said disposing the second dielectric comprises printing the second dielectric, and wherein said disposing the second ground plane comprises printing the second ground plane.

3. The method of claim 1 , wherein said disposing the stripline comprises extending the stripline to contact at least one pad of the electronics component.

4. The method of claim 1 , wherein said disposing the second dielectric comprises disposing the second dielectric over the electronics component.

5. The method of claim 1 , further comprising interconnecting the first ground plane and the second ground plane.

6. The method of claim 5 , wherein said interconnecting comprises interconnecting the first ground plane and the second ground plane with interconnects.

7. The method of claim 1 , further comprising interconnecting the electronics component and the second ground plane.

8. The method of claim 7 , wherein said interconnecting comprises interconnecting a ground paddle of the electronics component and the second ground plane with interconnects.

9. The method of claim 1 , further comprising:
interconnecting the first ground plane and the second ground plane with first interconnects; and
interconnecting a ground paddle of the electronics component and the second ground plane with second interconnects.

10. The method of claim 1 , wherein said disposing the first ground plane comprises refraining from disposing the first ground plane over the electronics component.

11. An electronics assembly, comprising:
a substrate;
an electronics component attached to the substrate;
one or more dielectric ramps disposed on the substrate along at least a portion of a perimeter of the electronics component;
a first ground plane disposed over the substrate and the one or more dielectric ramps;
a first dielectric disposed over the first ground plane;
a stripline disposed over the first dielectric;
a second dielectric disposed over the stripline and the first dielectric; and
a second ground plane disposed over the second dielectric.

12. The electronics assembly of claim 11 , wherein the stripline contacts at least one pad of the electronics component.

13. The electronics assembly of claim 11 , wherein the second dielectric is disposed over the electronics component.

14. The electronics assembly of claim 11 , wherein the first ground plane and the second ground plane are interconnected.

15. The electronics assembly of claim 14 , further comprising interconnects that interconnect the first ground plane and the second ground plane.

16. The electronics assembly of claim 11 , wherein the electronics component and the second ground plane are interconnected.

17. The electronics assembly of claim 16 , further comprising interconnects that interconnect a ground paddle of the electronics component and the second ground plane.

18. The electronics assembly of claim 11 , further comprising:
first interconnects that interconnect the first ground plane and the second ground plane; and
second interconnects that interconnect a ground paddle of the electronics component and the second ground plane.

19. The electronics assembly of claim 11 , wherein the first ground plane comprises does not extend over the electronics component.

20. A method of forming an electronics assembly, the method comprising:
providing a substrate;
attaching an electronics component to the substrate;
printing one or more dielectric ramps on the substrate along at least a portion of a perimeter of the electronics component;
printing a first ground plane over the substrate and the one or more dielectric ramps, wherein said printing the first ground plane comprises refraining from disposing the first ground plane over the electronics component;
printing a first dielectric over the first ground plane;
printing a stripline over the first dielectric, wherein said printing the stripline comprises extending the stripline to contact at least one pad of the electronics component;
printing a second dielectric over the stripline, the first dielectric, and the electronics component;
printing a second ground plane over the second dielectric;
interconnecting the first ground plane and the second ground plane with first interconnects; and
interconnecting a ground paddle of the electronics component and the second ground plane with second interconnects.

Assignees

• Boeing Co

Inventors

• Rogers John E

Classifications

• H05K1/189

  characterised by the use of flexible or folded printed circuits · CPC title

• H05K2201/0723

  provided by an inner layer of PCB · CPC title

• H05K1/0219

  Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors · CPC title

• H05K1/185 Primary

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K3/4664

  Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders (H05K3/4647 takes precedence) · CPC title